Server Virtualization

Virtualisoinnin ideana on kuvata tietotekniikkaan liittyvät laiteresurssit ryhminä. Kun jonkin tehtävän suoritukseen tarvitaan resursseja, ne kerätään erikseen jokaisesta ryhmästä. Virtualisoinnin yksi osa-alue on palvelimen tai palvelinten virtualisointi, jossa pyritään hyödyntämään palvelinlaitteisto mahdollisimman tehokkaasti. Tehokkuus saavutetaan käyttämällä erillisiä instansseja, joita kutsutaan virtuaalikoneiksi. Tässä diplomityössä esitellään ja verrataan erilaisia palvelinten virtualisointimalleja ja tekniikoita, joita voidaan käyttää IA-32 arkkitehtuurin kanssa. Eroa virtualisoinnin ja eri partitiointitekniikoiden välillä tarkastellaan erikseen. Lisäksi muutoksia, joita palvelinten virtualisointi aiheuttaa infrastruktuuriin, ympäristöön ja laitteistoon käsitellään yleisellä tasolla. Teorian oikeellisuutta todistettiin suorittamalla useita testejä käyttäen kahta eri virtualisointiohjelmistoa. Testien perusteella palvelinten virtualisointi vähentää suorituskykyä ja luo ympäristön, jonka hallitseminen on vaikeampaa verrattuna perinteiseen ympäristöön. Myös tietoturvaa on katsottava uudesta näkökulmasta, sillä fyysistä eristystä ei virtuaalikoneille voida toteuttaa. Jotta virtualisoinnista saataisiin mahdollisimman suuri hyöty tuotantoympäristössä, vaaditaan tarkkaa harkintaa ja suunnitelmallisuutta. Parhaat käyttökohteet ovat erilaiset testiympäristöt, joissa vaatimukset suorituskyvyn ja turvallisuuden suhteen eivät ole niin tarkat.

Kolmiulotteinen visualisointi mikromaailman konenäköjärjestelmässä

Työssä oli tarkoituksena saada toteutettua kolmiulotteiseen visualisointiin soveltuva ohjelmisto mikrokokoluokkaa olevien kappaleiden konenäköjärjestelmään. Työssä jouduttiin myös jatkokehittämään menetelmää kolmiulotteisen kuvan hankkimiseksi yhdellä kameralla mikrokokoisesta kohteesta. Kohteen kolmiulotteisella kuvalla voitaisiin suorittaa automaattista järjestelmäohjausta. Työssä tutkittiin ja selvitettiin laitteistolla saavutettavia tarkkuuksia ja nopeuksia, sen soveltamiseksi esimerkiksi mikromanipulaattorin ohjaamiseen. Lisäksi tutkittiin erilaisia kohteita joissa voitaisiin hyödyntää kolmiulotteista visualisointia. Tällaisia kohteita on kappaleiden laadunvalvonnassa tai niiden tutkimisessa ja esittämisessä. Syvyystiedon keräävällä menetelmällä oli saavutettava riittävä nopeus, jotta sillä voitaisiin tarvittaessa ohjata reaaliaikaisesti toimilaitteita. Menetelmänä käytettiin "Depth from Focusing" -menetelmää, johon VTT:llä oli jo aiemmin kehitetty automaattinen fokusointiohjelmisto. Työn puitteissa suoritettiin laitteisto- ja menetelmäkehitystä järjestelmän nopeuttamiseksi. Visualisoinnin toteuttamisen eri mahdollisuuksia kartoitettiin ja sellainen toteutettiin rakennettuun konenäköjärjestelmään.

Java Mobile Media API porting in Symbian Operating System

Työssä tutkitaan, kuinka Symbian käyttöjärjestelmälle voidaan tehdä siirrettäviä ohjelmia. Työssä käydään läpi menetelmiä, jotka helpottavat ohjelmistojen siirrettävyyttä uudelle alustalle. Uuteen älypuhelimeen voi tulla monia uusia komponentteja. Laite voi muuttua piiritasolla, käyttöjärjestelmästä voi tulla uusi versio sekä siirrettävästä ohjelmasta voi tulla uusi versio. Kaikki nämä vaikuttavat ohjelman siirrettävyyteen. Työssä tehtiin Java-rajapinnan siirto uudelle alustalle. Prosessin aikana löydettiin tärkeitä tekijöitä, jotka vaikuttavat ohjelmiston siirrettävyyteen. Siirrettävyys sinänsä pitäisi ottaa huomioon ohjelmistoprosessin jokaisessa vaiheessa. Älypuhelimista tulee jatkuvasti uusia versioita. Tämä tekee ohjelmien siirrettävyydestä hyvin tärkeän tekijän ohjelmistojen suunnittelussa. Hyvin suunniteltu ohjelma on helpompi ylläpitää, päivättää ja siirtää myöhemmin.

A System-Level Simulation Model for a Protocol Processor

As the development of integrated circuit technology continues to follow Moore’s law the complexity of circuits increases exponentially. Traditional hardware description languages such as VHDL and Verilog are no longer powerful enough to cope with this level of complexity and do not provide facilities for hardware/software codesign. Languages such as SystemC are intended to solve these problems by combining the powerful expression of high level programming languages and hardware oriented facilities of hardware description languages. To fully replace older languages in the desing flow of digital systems SystemC should also be synthesizable. The devices required by modern high speed networks often share the same tight constraints for e.g. size, power consumption and price with embedded systems but have also very demanding real time and quality of service requirements that are difficult to satisfy with general purpose processors. Dedicated hardware blocks of an application specific instruction set processor are one way to combine fast processing speed, energy efficiency, flexibility and relatively low time-to-market. Common features can be identified in the network processing domain making it possible to develop specialized but configurable processor architectures. One such architecture is the TACO which is based on transport triggered architecture. The architecture offers a high degree of parallelism and modularity and greatly simplified instruction decoding. For this M.Sc.(Tech) thesis, a simulation environment for the TACO architecture was developed with SystemC 2.2 using an old version written with SystemC 1.0 as a starting point. The environment enables rapid design space exploration by providing facilities for hw/sw codesign and simulation and an extendable library of automatically configured reusable hardware blocks. Other topics that are covered are the differences between SystemC 1.0 and 2.2 from the viewpoint of hardware modeling, and compilation of a SystemC model into synthesizable VHDL with Celoxica Agility SystemC Compiler. A simulation model for a processor for TCP/IP packet validation was designed and tested as a test case for the environment.

RTOS Framework for Real-Time Control System

This thesis is done as a complementary part for the active magnet bearing (AMB) control software development project in Lappeenranta University of Technology. The main focus of the thesis is to examine an idea of a real-time operating system (RTOS) framework that operates in a dedicated digital signal processor (DSP) environment. General use real-time operating systems do not necessarily provide sufficient platform for periodic control algorithm utilisation. In addition, application program interfaces found in real-time operating systems are commonly non-existent or provided as chip-support libraries, thus hindering platform independent software development. Hence, two divergent real-time operating systems and additional periodic extension software with the framework design are examined to find solutions for the research problems. The research is discharged by; tracing the selected real-time operating system, formulating requirements for the system, and designing the real-time operating system framework (OSFW). The OSFW is formed by programming the framework and conjoining the outcome with the RTOS and the periodic extension. The system is tested and functionality of the software is evaluated in theoretical context of the Rate Monotonic Scheduling (RMS) theory. The performance of the OSFW and substance of the approach are discussed in contrast to the research theme. The findings of the thesis demonstrates that the forged real-time operating system framework is a viable groundwork solution for periodic control applications.

A Model-Based Development and Verification Framework for Distributed System-on-Chip Architecture

The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.

An EDTA-β-cyclodextrin adsorbent for the adsorption of rare earth elements and its application in preconcentration of ultratrace rare earth elements from seawater

The objectives of this work were synthesizing an EDTA-β-CD adsorbent and investigating its adsorption potential and applications in preconcentration of REEs from aqueous phase. The adsorption capacity of EDTA-β-CD was investigated. The adsorption studies were performed by batch techniques both in one- and multi-component systems. The effects of pH, contact time and initial concentration were evaluated. The analytical detection methods and characterization methods were presented. EDTA-β-CD adsorbent was synthesized successfully with high EDTA coverage. The maximum REEs uptake was 0.310 mmol g-1 for La(III), 0.337 mmol g-1 for Ce(III) and 0.353 mmol g-1 for Eu(III), respectively. The kinetics of REEs onto EDTA-β-CD fitted well to pseudo-second-order model and the adsorption rate was affected by intra-particle diffusion. The experimental data of one component studies fitted to Langmuir isotherm model indicating the homogeneous surface of the adsorbent. The extended Sips model was applicable for the isotherm studies in three-component system. The electrostatic interaction, chelation and complexation were all involved in the adsorption mechanism. The preconcentration of RE ions and regeneration of EDTA-β-CD were successful. Overall, EDTA-β-CD is an effective adsorbent in adsorption and preconcentration of REEs.

Experimentation on Wind Powered Hydraulic Heating System

It is common knowledge of the world’s dependency on fossil fuel for energy, its unsustainability on the long run and the changing trend towards renewable energy as an alternative energy source. This aims to cut down greenhouse gas emission and its impact on the rate of ecological and climatic change. Quite remarkably, wind energy has been one of many focus areas of renewable energy sources and has attracted lots of investment and technological advancement. The objective of this research is to explore wind energy and its application in household heating. This research aims at applying experimental approach in real time to study and verify a virtually simulated wind powered hydraulic house heating system. The hardware components comprise of an integrated hydraulic pump, flow control valve, hydraulic fluid and other hydraulic components. The system design and control applies hardware in-the-loop (HIL) simulation setup. Output signal from the semi-empirical turbine modelling controls the integrated motor to generate flow. Throttling the volume flow creates pressure drop across the valve and subsequently thermal power in the system to be outputted using a heat exchanger. Maximum thermal power is achieved by regulating valve orifice to achieve optimum system parameter. Savonius rotor is preferred for its low inertia, high starting torque and ease of design and maintenance characteristics, but lags in power efficiency. A prototype turbine design is used; with power output in range of practical Savonius turbine. The physical mechanism of the prototype turbine’s augmentation design is not known and will not be a focus in this study.

Control of a line robot system with Embedded Linux

Many, if not all, aspects of our everyday lives are related to computers and control. Microprocessors and wireless communications are involved in our lives. Embedded systems are an attracting field because they combine three key factors, small size, low power consumption and high computing capabilities. The aim of this thesis is to study how Linux communicates with the hardware, to answer the question if it is possible to use an operating system like Debian for embedded systems and finally, to build a Mechatronic real time application. In the thesis a presentation of Linux and the Xenomai real time patch is given, the bootloader and communication with the hardware is analyzed. BeagleBone the evaluation board is presented along with the application project consisted of a robot cart with a driver circuit, a line sensor reading a black line and two Xbee antennas. It makes use of Xenomai threads, the real time kernel. According to the obtained results, Linux is able to operate as a real time operating system. The issue of future research is the area of embedded Linux is also discussed.

The Design and Implementation of a SD Card File System

SD card (Secure Digital Memory Card) is widely used in portable storage medium. Currently, latest researches on SD card, are mainly SD card controller based on FPGA (Field Programmable Gate Array). Most of them are relying on API interface (Application Programming Interface), AHB bus (Advanced High performance Bus), etc. They are dedicated to the realization of ultra high speed communication between SD card and upper systems. Studies about SD card controller, really play a vital role in the field of high speed cameras and other sub-areas of expertise. This design of FPGA-based file systems and SD2.0 IP (Intellectual Property core) does not only exhibit a nice transmission rate, but also achieve the systematic management of files, while retaining a strong portability and practicality. The file system design and implementation on a SD card covers the main three IP innovation points. First, the combination and integration of file system and SD card controller, makes the overall system highly integrated and practical. The popular SD2.0 protocol is implemented for communication channels. Pure digital logic design based on VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), integrates the SD card controller in hardware layer and the FAT32 file system for the entire system. Secondly, the document management system mechanism makes document processing more convenient and easy. Especially for small files in batch processing, it can ease the pressure of upper system to frequently access and process them, thereby enhancing the overall efficiency of systems. Finally, digital design ensures the superior performance. For transmission security, CRC (Cyclic Redundancy Check) algorithm is for data transmission protection. Design of each module is platform-independent of macro cells, and keeps a better portability. Custom integrated instructions and interfaces may facilitate easily to use. Finally, the actual test went through multi-platform method, Xilinx and Altera FPGA developing platforms. The timing simulation and debugging of each module was covered. Finally, Test results show that the designed FPGA-based file system IP on SD card can support SD card, TF card and Micro SD with 2.0 protocols, and the successful implementation of systematic management for stored files, and supports SD bus mode. Data read and write rates in Kingston class10 card is approximately 24.27MB/s and 16.94MB/s.