Thermal Stress in a Roll-to-Roll Printed Electronics Substrate

The Roll-to-Roll process makes it possible to print electronic products continuously onto a uniform substrate. Printing components on flexible surfaces can bring down the costs of simple electronic devices such as RFID tags, antennas and transistors. The possibility of quickly printing flexible electronic components opens up a wide array of novel products previously too expensive to produce on a large scale. Several different printing methods can be used in Roll-to-Roll printing, such as gravure, spray, offset, flexographic and others. Most of the methods can also be mixed in one production line. Most of them still require years of research to reach a significant commercial level. The research for this thesis was carried out at the Konkuk University Flexible Display Research Center (KU-FDRC) in Seoul, Korea. A system using Roll-to-Roll printing requires that the motion of the web can be controlled in every direction in order to align different layers of ink properly. Between printers the ink is dried with hot air. The effects of thermal expansion on the tension of the web are studied in this work, and a mathematical model was constructed on Matlab and Simulink. Simulations and experiments lead to the conclusion that the thermal expansion of the web has a great influence on the tension of the web. Also, experimental evidence was gained that the particular printing machine used for these experiments at KU-FDRC may have a problem in controlling the speeds of the cylinders which pull the web.

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.

Paper for printed electronics and functionality

Mass-produced paper electronics (large area organic printed electronics on paper-based substrates, “throw-away electronics”) has the potential to introduce the use of flexible electronic applications in everyday life. While paper manufacturing and printing have a long history, they were not developed with electronic applications in mind. Modifications to paper substrates and printing processes are required in order to obtain working electronic devices. This should be done while maintaining the high throughput of conventional printing techniques and the low cost and recyclability of paper. An understanding of the interactions between the functional materials, the printing process and the substrate are required for successful manufacturing of advanced devices on paper. Based on the understanding, a recyclable, multilayer-coated paper-based substrate that combines adequate barrier and printability properties for printed electronics and sensor applications was developed in this work. In this multilayer structure, a thin top-coating consisting of mineral pigments is coated on top of a dispersion-coated barrier layer. The top-coating provides well-controlled sorption properties through controlled thickness and porosity, thus enabling optimizing the printability of functional materials. The penetration of ink solvents and functional materials stops at the barrier layer, which not only improves the performance of the functional material but also eliminates potential fiber swelling and de-bonding that can occur when the solvents are allowed to penetrate into the base paper. The multi-layer coated paper under consideration in the current work consists of a pre-coating and a smoothing layer on which the barrier layer is deposited. Coated fine paper may also be used directly as basepaper, ensuring a smooth base for the barrier layer. The top layer is thin and smooth consisting of mineral pigments such as kaolin, precipitated calcium carbonate, silica or blends of these. All the materials in the coating structure have been chosen in order to maintain the recyclability and sustainability of the substrate. The substrate can be coated in steps, sequentially layer by layer, which requires detailed understanding and tuning of the wetting properties and topography of the barrier layer versus the surface tension of the top-coating. A cost competitive method for industrial scale production is the curtain coating technique allowing extremely thin top-coatings to be applied simultaneously with a closed and sealed barrier layer. The understanding of the interactions between functional materials formulated and applied on paper as inks, makes it possible to create a paper-based substrate that can be used to manufacture printed electronics-based devices and sensors on paper. The multitude of functional materials and their complex interactions make it challenging to draw general conclusions in this topic area. Inevitably, the results become partially specific to the device chosen and the materials needed in its manufacturing. Based on the results, it is clear that for inks based on dissolved or small size functional materials, a barrier layer is beneficial and ensures the functionality of the printed material in a device. The required active barrier life time depends on the solvents or analytes used and their volatility. High aspect ratio mineral pigments, which create tortuous pathways and physical barriers within the barrier layer limit the penetration of solvents used in functional inks. The surface pore volume and pore size can be optimized for a given printing process and ink through a choice of pigment type and coating layer thickness. However, when manufacturing multilayer functional devices, such as transistors, which consist of several printed layers, compromises have to be made. E.g., while a thick and porous top-coating is preferable for printing of source and drain electrodes with a silver particle ink, a thinner and less absorbing surface is required to form a functional semiconducting layer. With the multilayer coating structure concept developed in this work, it was possible to make the paper substrate suitable for printed functionality. The possibility of printing functional devices, such as transistors, sensors and pixels in a roll-to-roll process on paper is demonstrated which may enable introducing paper for use in disposable “onetime use” or “throwaway” electronics and sensors, such as lab-on-strip devices for various analyses, consumer packages equipped with product quality sensors or remote tracking devices.

Research and development of III-V semiconductor surfaces for improved device interfaces

This thesis is devoted to understanding and improving technologically important III-V compound semiconductor (e.g. GaAs, InAs, and InSb) surfaces and interfaces for devices. The surfaces and interfaces of crystalline III-V materials have a crucial role in the operation of field-effect-transistors (FET) and highefficiency solar-cells, for instance. However, the surfaces are also the most defective part of the semiconductor material and it is essential to decrease the amount of harmful surface or interface defects for the next-generation III-V semiconductor device applications. Any improvement in the crystal ordering at the semiconductor surface reduces the amount of defects and increases the material homogeneity. This is becoming more and more important when the semiconductor device structures decrease to atomic-scale dimensions. Toward that target, the effects of different adsorbates (i.e., Sn, In, and O) on the III-V surface structures and properties have been investigated in this work. Furthermore, novel thin-films have been synthesized, which show beneficial properties regarding the passivation of the reactive III-V surfaces. The work comprises ultra-high-vacuum (UHV) environment for the controlled fabrication of atomically ordered III-V(100) surfaces. The surface sensitive experimental methods [low energy electron diffraction (LEED), scanning tunneling microscopy/spectroscopy (STM/STS), and synchrotron radiation photoelectron spectroscopy (SRPES)] and computational density-functionaltheory (DFT) calculations are utilized for elucidating the atomic and electronic properties of the crucial III-V surfaces. The basic research results are also transferred to actual device tests by fabricating metal-oxide-semiconductor capacitors and utilizing the interface sensitive measurement techniques [capacitance voltage (CV) profiling, and photoluminescence (PL) spectroscopy] for the characterization. This part of the thesis includes the instrumentation of home-made UHV-compatible atomic-layer-deposition (ALD) reactor for growing good quality insulator layers. The results of this thesis elucidate the atomic structures of technologically promising Sn- and In-stabilized III-V compound semiconductor surfaces. It is shown that the Sn adsorbate induces an atomic structure with (1×2)/(1×4) surface symmetry which is characterized by Sn-group III dimers. Furthermore, the stability of peculiar ζa structure is demonstrated for the GaAs(100)-In surface. The beneficial effects of these surface structures regarding the crucial III-V oxide interface are demonstrated. Namely, it is found that it is possible to passivate the III-V surface by a careful atomic-scale engineering of the III-V surface prior to the gate-dielectric deposition. The thin (1×2)/(1×4)-Sn layer is found to catalyze the removal of harmful amorphous III-V oxides. Also, novel crystalline III-V-oxide structures are synthesized and it is shown that these structures improve the device characteristics. The finding of crystalline oxide structures is exploited by solving the atomic structure of InSb(100)(1×2) and elucidating the electronic structure of oxidized InSb(100) for the first time.

Synthesis, characterization and chemical sensor application of conducting polymers

Polymeric materials that conduct electricity are highly interesting for fundamental studies and beneficial for modern applications in e.g. solar cells, organic field effect transistors (OFETs) as well as in chemical and bio‐sensing. Therefore, it is important to characterize this class of materials with a wide variety of methods. This work summarizes the use of electrochemistry also in combination with spectroscopic methods in synthesis and characterization of electrically conducting polymers and other π‐conjugated systems. The materials studied in this work are intended for organic electronic devices and chemical sensors. Additionally, an important part of the presented work, concerns rational approaches to the development of water‐based inks containing conducting particles. Electrochemical synthesis and electroactivity of conducting polymers can be greatly enhanced in room temperature ionic liquids (RTILs) in comparison to conventional electrolytes. Therefore, poly(para‐phyenylene) (PPP) was electrochemically synthesized in the two representative RTILs: bmimPF6 and bmiTf2N (imidazolium and pyrrolidinium‐based salts, respectively). It was found that the electrochemical synthesis of PPP was significantly enhanced in bmimPF6. Additionally, the results from doping studies of PPP films indicate improved electroactivity in bmimPF6 during oxidation (p‐doping) and in bmiTf2N in the case of reduction (n‐doping). These findings were supported by in situ infrared spectroscopy studies. Conducting poly(benzimidazobenzophenanthroline) (BBL) is a material which can provide relatively high field‐effect mobility of charge carriers in OFET devices. The main disadvantage of this n‐type semiconductor is its limited processability. Therefore in this work BBL was functionalized with poly(ethylene oxide) PEO, varying the length of side chains enabling water dispersions of the studied polymer. It was found that functionalization did not distract the electrochemical activity of the BBL backbone while the processability was improved significantly in comparison to conventional BBL. Another objective was to study highly processable poly(3,4‐ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) water‐based inks for controlled patterning scaled‐down to nearly a nanodomain with the intention to fabricate various chemical sensors. Developed PEDOT:PSS inks greatly improved printing of nanoarrays and with further modification with quaternary ammonium cations enabled fabrication of PEDOT:PSS‐based chemical sensors for lead (II) ions with enhanced adhesion and stability in aqueous environments. This opens new possibilities for development of PEDOT:PSS films that can be used in bio‐related applications. Polycyclic aromatic hydrocarbons (PAHs) are a broad group of π‐conjugated materials consisting of aromatic rings in the range from naphthalene to even hundred rings in one molecule. The research on this type of materials is intriguing, due to their interesting optical properties and resemblance of graphene. The objective was to use electrochemical synthesis to yield relatively large PAHs and fabricate electroactive films that could be used as template material in chemical sensors. Spectroscopic, electrochemical and electrical investigations evidence formation of highly stable films with fast redox response, consisting of molecules with 40 to 60 carbon atoms. Additionally, this approach in synthesis, starting from relatively small PAH molecules was successfully used in chemical sensor for lead (II).

Power semiconductor nonlinearities in active du/dt output filtering

This doctoral thesis introduces an improved control principle for active du/dt output filtering in variable-speed AC drives, together with performance comparisons with previous filtering methods. The effects of power semiconductor nonlinearities on the output filtering performance are investigated. The nonlinearities include the timing deviation and the voltage pulse waveform distortion in the variable-speed AC drive output bridge. Active du/dt output filtering (ADUDT) is a method to mitigate motor overvoltages in variable-speed AC drives with long motor cables. It is a quite recent addition to the du/dt reduction methods available. This thesis improves on the existing control method for the filter, and concentrates on the lowvoltage (below 1 kV AC) two-level voltage-source inverter implementation of the method. The ADUDT uses narrow voltage pulses having a duration in the order of a microsecond from an IGBT (insulated gate bipolar transistor) inverter to control the output voltage of a tuned LC filter circuit. The filter output voltage has thus increased slope transition times at the rising and falling edges, with an opportunity of no overshoot. The effect of the longer slope transition times is a reduction in the du/dt of the voltage fed to the motor cable. Lower du/dt values result in a reduction in the overvoltage effects on the motor terminals. Compared with traditional output filtering methods to accomplish this task, the active du/dt filtering provides lower inductance values and a smaller physical size of the filter itself. The filter circuit weight can also be reduced. However, the power semiconductor nonlinearities skew the filter control pulse pattern, resulting in control deviation. This deviation introduces unwanted overshoot and resonance in the filter. The controlmethod proposed in this thesis is able to directly compensate for the dead time-induced zero-current clamping (ZCC) effect in the pulse pattern. It gives more flexibility to the pattern structure, which could help in the timing deviation compensation design. Previous studies have shown that when a motor load current flows in the filter circuit and the inverter, the phase leg blanking times distort the voltage pulse sequence fed to the filter input. These blanking times are caused by excessively large dead time values between the IGBT control pulses. Moreover, the various switching timing distortions, present in realworld electronics when operating with a microsecond timescale, bring additional skew to the control. Left uncompensated, this results in distortion of the filter input voltage and a filter self-induced overvoltage in the form of an overshoot. This overshoot adds to the voltage appearing at the motor terminals, thus increasing the transient voltage amplitude at the motor. This doctoral thesis investigates the magnitude of such timing deviation effects. If the motor load current is left uncompensated in the control, the filter output voltage can overshoot up to double the input voltage amplitude. IGBT nonlinearities were observed to cause a smaller overshoot, in the order of 30%. This thesis introduces an improved ADUDT control method that is able to compensate for phase leg blanking times, giving flexibility to the pulse pattern structure and dead times. The control method is still sensitive to timing deviations, and their effect is investigated. A simple approach of using a fixed delay compensation value was tried in the test setup measurements. The ADUDT method with the new control algorithm was found to work in an actual motor drive application. Judging by the simulation results, with the delay compensation, the method should ultimately enable an output voltage performance and a du/dt reduction that are free from residual overshoot effects. The proposed control algorithm is not strictly required for successful ADUDT operation: It is possible to precalculate the pulse patterns by iteration and then for instance store them into a look-up table inside the control electronics. Rather, the newly developed control method is a mathematical tool for solving the ADUDT control pulses. It does not contain the timing deviation compensation (from the logic-level command to the phase leg output voltage), and as such is not able to remove the timing deviation effects that cause error and overshoot in the filter. When the timing deviation compensation has to be tuned-in in the control pattern, the precalculated iteration method could prove simpler and equally good (or even better) compared with the mathematical solution with a separate timing compensation module. One of the key findings in this thesis is the conclusion that the correctness of the pulse pattern structure, in the sense of ZCC and predicted pulse timings, cannot be separated from the timing deviations. The usefulness of the correctly calculated pattern is reduced by the voltage edge timing errors. The doctoral thesis provides an introductory background chapter on variable-speed AC drives and the problem of motor overvoltages and takes a look at traditional solutions for overvoltage mitigation. Previous results related to the active du/dt filtering are discussed. The basic operation principle and design of the filter have been studied previously. The effect of load current in the filter and the basic idea of compensation have been presented in the past. However, there was no direct way of including the dead time in the control (except for solving the pulse pattern manually by iteration), and the magnitude of nonlinearity effects had not been investigated. The enhanced control principle with the dead time handling capability and a case study of the test setup timing deviations are the main contributions of this doctoral thesis. The simulation and experimental setup results show that the proposed control method can be used in an actual drive. Loss measurements and a comparison of active du/dt output filtering with traditional output filtering methods are also presented in the work. Two different ADUDT filter designs are included, with ferrite core and air core inductors. Other filters included in the tests were a passive du/dtfilter and a passive sine filter. The loss measurements incorporated a silicon carbide diode-equipped IGBT module, and the results show lower losses with these new device technologies. The new control principle was measured in a 43 A load current motor drive system and was able to bring the filter output peak voltage from 980 V (the previous control principle) down to 680 V in a 540 V average DC link voltage variable-speed drive. A 200 m motor cable was used, and the filter losses for the active du/dt methods were 111W–126 W versus 184 W for the passive du/dt. In terms of inverter and filter losses, the active du/dt filtering method had a 1.82-fold increase in losses compared with an all-passive traditional du/dt output filter. The filter mass with the active du/dt method was 17% (2.4 kg, air-core inductors) compared with 14 kg of the passive du/dt method filter. Silicon carbide freewheeling diodes were found to reduce the inverter losses in the active du/dt filtering by 18% compared with the same IGBT module with silicon diodes. For a 200 m cable length, the average peak voltage at the motor terminals was 1050 V with no filter, 960 V for the all-passive du/dt filter, and 700 V for the active du/dt filtering applying the new control principle.

Reducing contact resistance in graphene devices

In this thesis, the contact resistance of graphene devices was investigated because high contact resistance is detrimental to the performance of graphene field-effect transistors (GFET). Method for increasing so-called edge-contact area was applied in device fabrication process, as few nanometers thick Ni layer was used as a catalytic etchant during the annealing process. Finally, Ni was also used as a metal for contact. GFETs were fabricated using electron beam lithography using graphene fabricated by chemical vapor deposition (CVD). Critical part of the fabrication process was to preserve the high quality of the graphene channel while etching the graphene at contact areas with Ni during the annealing. This was achieved by optimizing the combination of temperature and gas flows. The structural properties of graphene were studied using scanning electron microscopy, scanning confocal μ-Raman spectroscopy and optical microscopy. Evaluation of electric transport properties including contact resistance was carried out by transmission line method and four-probe method. The lowest contact resistance found was about at 350 Ωμm. In addition, different methods to transfer CVD graphene synthesized on copper were studied. Typical method using PMMA as a supporting layer leaves some residues after its removal, thus effecting on the performance of a graphene devices. In a metal assisted transfer method, metal is used as an interfacial layer between PMMA and graphene. This allows more effective removal of PMMA. However, Raman spectra of graphene transferred by metal assisted method showed somewhat lower quality than the PMMA assisted method

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

Spectroscopic Studies of III-V Semiconductor Materials for Improved Devices

Defects in semiconductor crystals and at their interfaces usually impair the properties and the performance of devices. These defects include, for example, vacancies (i.e., missing crystal atoms), interstitials (i.e., extra atoms between the host crystal sites), and impurities such as oxygen atoms. The defects can decrease (i) the rate of the radiative electron transition from the conduction band to the valence band, (ii) the amount of charge carriers, and (iii) the mobility of the electrons in the conduction band. It is a common situation that the presence of crystal defects can be readily concluded as a decrease in the luminescence intensity or in the current flow for example. However, the identification of the harmful defects is not straightforward at all because it is challenging to characterize local defects with atomic resolution and identification. Such atomic-scale knowledge is however essential to find methods for reducing the amount of defects in energy-efficient semiconductor devices. The defects formed in thin interface layers of semiconductors are particularly difficult to characterize due to their buried and amorphous structures. Characterization methods which are sensitive to defects often require well-defined samples with long range order. Photoelectron spectroscopy (PES) combined with photoluminescence (PL) or electrical measurements is a potential approach to elucidate the structure and defects of the interface. It is essential to combine the PES with complementary measurements of similar samples to relate the PES changes to changes in the interface defect density. Understanding of the nature of defects related to III-V materials is relevant to developing for example field-effect transistors which include a III-V channel, but research is still far from complete. In this thesis, PES measurements are utilized in studies of various III-V compound semiconductor materials. PES is combined with photoluminescence measurements to study the SiO2/GaAs, SiNx/GaAs and BaO/GaAs interfaces. Also the formation of novel materials InN and photoluminescent GaAs nanoparticles are studied. Finally, the formation of Ga interstitial defects in GaAsN is elucidated by combining calculational results with PES measurements.

Kartoitus kloori-alkalitehtaan tuotantokapasiteetin kasvattamisesta / Kemira Chemicals Oy Joutseno

Kemira Chemicals Oy:n Joutsenon kloori-alkalitehtaalla valmistetaan elektrolyysin avulla lipeää, suolahappoa, natriumhypokloriittia ja vetyä. Tämän työn tavoitteena on kartoittaa kloori-alkalitehtaan tuotantokapasiteetin kasvatuksen yhteydessä esiin tulevat pullonkaulat, lähitulevaisuuden kunnossapitotarpeet sekä parhaat käytettävissä olevat teknologiavaihtoehdot kloori-alkalitehtaan osa-alueille, joihin tuotantokapasiteetin kasvatuspaineet kohdistuvat: elektrolyysi, lipeän haihdutus ja suolahappopolttimet. Pullonkaulojen kartoittaminen toteutettiin rakentamalla taulukkolaskentamalli kloori-alkalitehtaan prosesseista. Mallin avulla simuloitiin elektrolyysin kloorin tuotantoa, jota kasvatettiin asteittain 54 kt:sta/a aina 100 kt:iin/a asti ja tutkittiin prosessien käyttäytymistä. Tarkastelun pohjalta havaittiin, että kloorin tuotantoa kasvattaessa, tulee lisätä myös tuotantokapasiteettia suolahapon valmistukseen, elektrolyysiin, demineralisoidun veden valmistukseen ja lipeän haihdutuslaitokseen sekä suolahapon ja lipeän varastointikapasiteetteihin. Vaihtoehtoiset teknologiat määritettiin kirjallisuudesta ja laitetoimittajien esitteistä. Lähivuosien kunnossapitotarpeet kartoitettiin haastattelemalla tehtaan henkilökuntaa. Työstä eskaloitui useita jatkotutkimuskohteita, joita ovat bipolaari-teknologian soveltuvuus Joutsenon kloori-alkalitehtaalle, uusien HCl-polttimien esisuunnittelu, höyryn käytön tehostaminen nykyisessä lipeän haihdutuslaitoksessa sekä uusien haihdutusteknologioiden soveltuvuus Joutsenon kloori-alkalitehtaalle, höyry- ja jäähdytysverkostojen kartoitukset sekä demineralisoidun veden valmistuskapasiteetin kasvattaminen.

Pienjännitteisen tasasähkönjakelun hyödyntäminen ja siihen liittyvä tutkimus maailmalla

Tässä kandidaatintyössä selvitetään kirjallisuustutkimuksena, minkälaista tutkimusta maailmalla on tehty liittyen pienjännitteiseen tasasähkönjakeluun, sekä missä sovelluskohteissa sitä hyödynnetään. Työssä esitetään yleisimmät järjestelmärakenteet ja sovelluskohteet sekä organisaatiot, joiden on havaittu tutkivan tasasähkönjakelua kiinteistöissä, microgrideissä tai julkisessa sähkönjakelussa. Katsauksen perusteella havaittiin, että maailmalla on tehty erityisesti laskennallisia tutkimuksia ja simulointeja liittyen pienjännitteiseen tasasähkönjakeluun. Näkökulma on pääasiassa ollut kiinteistöissä ja microgrideissä, vähäisemmässä määrin myös julkisissa sähkönjakeluverkoissa. Pienjännitteistä tasasähkönjakelua hyödynnetään, tai ainakin voitaisiin hyödyntää näissä kohteissa. Pääasiassa konseptilla on pyritty hakemaan kustannussäästöjä ja toisaalta parantamaan hyötysuhdetta. Ympäri maailmaa on käynnissä pilottihankkeita sekä kiinteistöihin, että julkiseen sähkönjakeluun liittyen. Bipolaarinen ratkaisu näytti olevan yleisempi. Käytetyt ja tutkitut jännitetasot vaihtelivat riippuen sovelluskohteesta – kiinteistön sisällä oli käytössä tasot pienoisjännitteestä aina 350–400 VDC jännitetasoon asti, ja sama 350–400 VDC oli selvästi suosittu jännitealue myös jakeluverkossa, mutta myös korkeampia jännitteitä, kuten 700–750 VDC, oli käytössä.

Hardware design of a multiconverter for hybrid vehicle applications

Hybridiajoneuvosovellukset vaativat usein sekä korkea- että matalajännitejärjestelmän. Korkeajännitejärjestelmä sisältää yleensä energiavaraston, joka on joko superkondansaattori tai korkeajänniteakusto, dieselgeneraattorin tai range extenderin ja ajokäytön. Korkeajännitejärjestelmään liitetään usein myös erilaisia apukäyttöjä kuten kompressoreita ja hydraulipumppuja. Matalajännitejärjelmä koostuu yleensä ohjausyksiköistä, ajovaloista, yms. laitteista. Perinteisesti matalajännitejärjestelmää on syötetty dieselmoottorin laturista, mutta korkeajännitejärjestelmien myötä DC/DC-hakkurin käyttäminen korkea- ja matalajännitejärjestelmien välillä on herättänyt kiinnostusta, koska tällöin laturin voisi poistaa ja matalajänniteakustoa pienentää. Tässä työssä kuvatun monilähöisen tehonmuokkaimen invertterisilta soveltuu apukäyttöjen ajamiseen, ja erotettu DC/DC-hakkuri matalajännitejärjestelmän syöttämiseen. Tässä työssä käydään läpi edellä mainitun tehonmuokkaimen suunnittelu, keskittyen eritoten laitteen korkeajänniteosien mitoitukseen ja termiseen suunniteluun. DC/DC-hakkurin osalta perinteisiä piistä valmistettuja IGBT transistoreja vertaillaan piikarbidi MOSFET transistoreihin. Lämpömallilaskujen paikkaansapitävyyttä tutkitaan suorittamalla prototyyppilaitteelle hyötysuhdemittaus, jonka tuloksia verrataan laskettuihin tuloksiin. Lämpömallin parannusmahdollisuuksia käsitellään myös hyötysuhdemittauksen tulosten perusteella.

Observations of Acoustic Emission in Power Semiconductors

Industrial, electrical power generation, and transportation systems, to name but a few, rely heavily on power electronics to control and convert electrical power. Each of these systems, when encountering an unexpected failure, can cause significant financial losses, or even an emergency. A condition monitoring system would help to alleviate these concerns, but for the time being, there is no generally accepted and widely adopted method for power electronics. Acoustic emission is used as a failure precursor in many applications, but it has not been studied in power electronics so far. In this doctoral dissertation, observations of acoustic emission in power semiconductor components are presented. The acoustic emissions are caused by the switching operation and failure of power transistors. Three types of acoustic emission are observed. Furthermore, aspects related to the measurement and detection of acoustic phenomena are discussed. These include sensor performance and mechanical construction of experimental setups. The results presented in this dissertation are the outset of a research program where it will be determined whether an acoustic-emission-based condition monitoring method can be developed.

D-luokan audiovahvistimen särö ja kohina

Tämän kandidaatintyön aiheena on D-luokan audiovahvistimen särö ja kohina. Tarkoituksena on selvittää vahvistinluokan merkittävin särö- ja kohinamekanismi, sekä arvioida, voidaanko häiriöitä vähentää lähdön suodattimella. Tutkimusmenetelminä on kirjallisuus ja simulointi. Aineistona on käytetty IEEE:ssä julkaistuja tieteelisiä artikkeleita, eri valmistajien laatimia ohjeita, sekä aihetta käsitteleviä kirjoja. Keskeisimmät tulokset olivat, että merkittävin särömekanismi on transistoreiden suoja-ajan aiheuttama vääristymä, sekä että merkittävin kohina syntyy modulaatiossa käytetystä kantoaallosta. Kantoaallon näkyvyyteen kuormassa voidaan vaikuttaa ulostulon alipäästösuodattimella. Suoja-ajan aiheuttama harmoninen kokonaissärö asettuu musiikin kaistanleveydelle, joten sitä ei voida poistaa suodattamalla.