Readout Electronics for Gas Electron Multiplier Detectors

The European Organization for Nuclear Research (CERN) operates the largest particle collider in the world. This particle collider is called the Large Hadron Collider (LHC) and it will undergo a maintenance break sometime in 2017 or 2018. During the break, the particle detectors, which operate around the particle collider, will be serviced and upgraded. Following the improvement in performance of the particle collider, the requirements for the detector electronics will be more demanding. In particular, the high amount of radiation during the operation of the particle collider sets requirements for the electronics that are uncommon in commercial electronics. Electronics that are built to function in the challenging environment of the collider have been designed at CERN. In order to meet the future challenges of data transmission, a GigaBit Transceiver data transmission module and an E-Link data bus have been developed. The next generation of readout electronics is designed to benefit from these technologies. However, the current readout electronics chips are not compatible with these technologies. As a result, in addition to new Gas Electron Multiplier (GEM) detectors and other technology, a new compatible chip is developed to function within the GEMs for the Compact Muon Solenoid (CMS) project. In this thesis, the objective was to study a data transmission interface that will be located on the readout chip between the E-Link bus and the control logic of the chip. The function of the module is to handle data transmission between the chip and the E-Link. In the study, a model of the interface was implemented with the Verilog hardware description language. This process was simulated by using chip design software by Cadence. State machines and operating principles with alternative possibilities for implementation are introduced in the E-Link interface design procedure. The functionality of the designed logic is demonstrated in simulation results, in which the implemented model is proven to be suitable for its task. Finally, suggestions that should be considered for improving the design have been presented.

LVDC power distribution system: computational modelling

In the doctoral dissertation, low-voltage direct current (LVDC) distribution system stability, supply security and power quality are evaluated by computational modelling and measurements on an LVDC research platform. Computational models for the LVDC network analysis are developed. Time-domain simulation models are implemented in the time-domain simulation environment PSCAD/EMTDC. The PSCAD/EMTDC models of the LVDC network are applied to the transient behaviour and power quality studies. The LVDC network power loss model is developed in a MATLAB environment and is capable of fast estimation of the network and component power losses. The model integrates analytical equations that describe the power loss mechanism of the network components with power flow calculations. For an LVDC network research platform, a monitoring and control software solution is developed. The solution is used to deliver measurement data for verification of the developed models and analysis of the modelling results. In the work, the power loss mechanism of the LVDC network components and its main dependencies are described. Energy loss distribution of the LVDC network components is presented. Power quality measurements and current spectra are provided and harmonic pollution on the DC network is analysed. The transient behaviour of the network is verified through time-domain simulations. DC capacitor guidelines for an LVDC power distribution network are introduced. The power loss analysis results show that one of the main optimisation targets for an LVDC power distribution network should be reduction of the no-load losses and efficiency improvement of converters at partial loads. Low-frequency spectra of the network voltages and currents are shown, and harmonic propagation is analysed. Power quality in the LVDC network point of common coupling (PCC) is discussed. Power quality standard requirements are shown to be met by the LVDC network. The network behaviour during transients is analysed by time-domain simulations. The network is shown to be transient stable during large-scale disturbances. Measurement results on the LVDC research platform proving this are presented in the work.

The improvement of enclosure protection class of power electronics device

Tässä diplomityössä tutkittiin vaihtoehtoja tehoelektroniikkalaitteiden kotelointiluokan kehittämiseksi. Haasteena paremman suojauksen suunnittelussa on laitteiden tuottama suuri määrä lämpöä, joka vaatii tehokkaan jäähdytyksen. Työn tuloksena saatu prototyyppi IP33 luokkaa varten täyttää standardissa SFS-EN 60529+A1 asetetut vaatimukset kyseiselle kotelointiluokalle. Rakenteessa ja valmistettavuudessa havaittiin muutama ongelma, jotka ovat korjattavissa pienillä muutoksilla. Korkeampia suojausluokkia varten testattiin IP54-luokiteltujen filtterituulettimien vaikutusta laitteen jäähdytykseen. Testien perusteella jäähdytysteho on riittävä ja filtterituulettimet todettiin toimivaksi ratkaisuksi korkeammille suojausluokille. Työn perusteella voidaan todeta, että nykyiset laitteet voidaan muokata vastaamaan IP33 luokan vaatimuksia kohtuullisen pienillä muutoksilla. Tätä korkeammat suojausluokat vaatisivat niin suuria muutoksia designiin, että todennäköisesti täysin uuden laitteen suunnittelu olis kannattavin vaihtoehto.

Modeling Front End Electronics for a Gas Electron Multiplier Detector

The Large Hadron Collider (LHC) in The European Organization for Nuclear Research (CERN) will have a Long Shutdown sometime during 2017 or 2018. During this time there will be maintenance and a possibility to install new detectors. After the shutdown the LHC will have a higher luminosity. A promising new type of detector for this high luminosity phase is a Triple-GEM detector. During the shutdown these detectors will be installed at the Compact Muon Solenoid (CMS) experiment. The Triple-GEM detectors are now being developed at CERN and alongside also a readout ASIC chip for the detector. In this thesis a simulation model was developed for the ASICs analog front end. The model will help to carry out more extensive simulations and also simulate the whole chip before the whole design is finished. The proper functioning of the model was tested with simulations, which are also presented in the thesis.

Spin-electromagnetic waves spectra in multiferroic heterostructures

This work devotes to the theoretical investigations of spin-electromagnetic waves (SEW) propagating in a thin-film multiferroic structures that were composed of a slot-line and structures with several ferrite films. In contrast to earlier works, the spin-electromagnetic waves in the investigated structures are originated from two different electrodynamics coupling. The first one is coupling of the electromagnetic wave localized mainly in the slot-line with the spin wave excited mostly in the ferrite film. The second one is coupling of two spin waves in the different ferrite films separated by a thin ferroelectric film. For theoretical analysis of SEWs propagation in such kind of structures theories of their eigen-wave spectra were developed. Spectra of SEW in the investigated structures were calculated and analyzed. The range of electric and magnetic tunability of dispersion characteristic were investigated. Spectra of SEW in the investigated multiferroic structures are used for investigation of transfer function of periodic structures.

Roll-to-roll atomic layer deposition process for flexible electronics applications

Atomic Layer Deposition (ALD) is the technology of choice where very thin and highquality films are required. Its advantage is its ability to deposit dense and pinhole-free coatings in a controllable manner. It has already shown promising results in a range of applications, e.g. diffusion barrier coatings for OLED displays, surface passivation layers for solar panels. Spatial Atomic Layer Deposition (SALD) is a concept that allows a dramatic increase in ALD throughput. During the SALD process, the substrate moves between spatially separated zones filled with the respective precursor gases and reagents in such a manner that the exposure sequence replicates the conventional ALD cycle. The present work describes the development of a high-throughput ALD process. Preliminary process studies were made using an SALD reactor designed especially for this purpose. The basic properties of the ALD process were demonstrated using the wellstudied Al2O3 trimethyl aluminium (TMA)+H2O process. It was shown that the SALD reactor is able to deposit uniform films in true ALD mode. The ALD nature of the process was proven by demonstrating self-limiting behaviour and linear film growth. The process behaviour and properties of synthesized films were in good agreement with previous ALD studies. Issues related to anomalous deposition at low temperatures were addressed as well. The quality of the coatings was demonstrated by applying 20 nm of the Al2O3 on to polymer substrate and measuring its moisture barrier properties. The results of tests confirmed the superior properties of the coatings and their suitability for flexible electronics encapsulation. Successful results led to the development of a pilot scale roll-to-roll coating system. It was demonstrated that the system is able to deposit superior quality films with a water transmission rate of 5x10-6 g/m2day at a web speed of 0.25 m/min. That is equivalent to a production rate of 180 m2/day and can be potentially increased by using wider webs. State-of-art film quality, high production rates and repeatable results make SALD the technology of choice for manufacturing ultra-high barrier coatings for flexible electronics.

Paper- and membrane-based ion-modulated electronics

Avhandlingen handlar om pappers- och membranbaserad jonmodulerad elektronik. Målet med forskningen har varit att utveckla billig, miljövänlig och brännbar elektronik, som kan användas i vardagliga engångsprodukter. Baskomponenterna som utvecklas och presenteras i avhandlingen är transistorer och kondensatorer. Mer komplicerad logisk kretselektronik demonstreras också med hjälp av dessa komponenter. Substraten som utnyttjas vid framställningen av dessa elektroniska komponenter är papper och membran. Dessa substrat är flexibla, hållbara, billiga, miljövänliga, etc. och därför väl anpassade för befintliga tryckteknologier. Själva baskomponenterna framställs sedan på dessa substrat genom att trycka flera skikt på varandra, där varje enskilt skikt är ett individuellt material. Detta är möjligt eftersom de organiska materialen som används i dessa komponenter är upplösta i ett lösningsmedel och kan därmed tryckas på samma sätt som ett vanligt bläck. Ett tredimensionellt objekt kan på detta sätt framställas. I avhandlingen presenteras flera olika typer av transistorer, men den gemensamma nämnaren bland dessa är att isolatorn är en jonledare. Denna, ganska ovanliga, transistormodellen har den stora fördelen att lågspänningskomponenter kan relativt enkelt framställas. Det som är speciellt med våra transistorer är att vi har använt miljövänliga jonledare. Detta, bl.a., leder till att våra komponenter visar både god prestanda, tillika som de är miljövänliga. I avhandlingen demonstrerar vi även tryckta superkondensatorer, en motsvarighet till laddningsbara batterier, konstruerade på papper med aktiverat kol och miljövänliga jonledare. De mest komplicerade logiska kretsar som demonstreras i denna avhandling är ring-oscillatorer och 1-bits-minnen konstruerade på papper. --------------------------------------------- Väitöskirja käsittelee paperille ja polymeerikalvolle tulostettua ionimoduloitua elektroniikkaa. Tutkimuksen tavoitteena oli kehittää edullista, ympäristöystävällistä ja polttokelpoista elektroniikkaa, jota voidaan käyttää esim. tavanomaisissa kertakäyttötuotteissa. Väitöskirjassa esitellään erilaisia transistoreita ja kondensaattoreita. Näitä elektronisia peruskomponentteja käyttäen demonstroidaan myös monimutkaisempia loogisia piirejä. Komponenttien valmistuksessa alustana käytettiin paperia ja polymeerikalvoa. Valitut alustat ovat joustavia ja kestäviä, ja ovat siksi hyvin yhteensopivia olemassa olevien tulostusmenetelmien kanssa. Peruskomponentit valmistettiin tulostamalla eri materiaaleja päällekkäin. Komponenteissa käytettävät orgaaniset aineet ovat liuenneessa muodossa musteessa, joka voidaan tulostaa samalla periaatteella kuin mikä tahansa normaali muste. Tällä menetelmällä voidaan valmistaa myös kolmiulotteisia tuotteita. Väitöskirjassa esitellään useita erityyppisiä transistoreita, joissa yhdistävänä tekijänä on ionisesti johtava eriste. Tällaista suhteellisen harvinaista transistorityyppiä käyttämällä voidaan mahdollistaa matala-jännitteisten komponenttien yksinkertainen valmistus. Valmistettujen transistoreiden etu on ionisten nesteiden ympäristöystävällisyys. Elektroniset komponentit ovat täten hyviä suorituskyvyltään, mutteivät haitallisia ympäristölle. Väitöskirjassa demonstroidaan myös tulostettujen superkondensaattoreiden, eli ladattavien paristojen vastineiden, valmistus paperille aktiivihiiltä ja ionisia nesteitä käyttäen. Kaikkein monimutkaisimmat loogiset piirit, jotka tässä väitöskirjassa esitellään, ovat rengasoskillaattorit sekä 1-bittinen paperille valmistettu muisti.