Reducing contact resistance in graphene devices

In this thesis, the contact resistance of graphene devices was investigated because high contact resistance is detrimental to the performance of graphene field-effect transistors (GFET). Method for increasing so-called edge-contact area was applied in device fabrication process, as few nanometers thick Ni layer was used as a catalytic etchant during the annealing process. Finally, Ni was also used as a metal for contact. GFETs were fabricated using electron beam lithography using graphene fabricated by chemical vapor deposition (CVD). Critical part of the fabrication process was to preserve the high quality of the graphene channel while etching the graphene at contact areas with Ni during the annealing. This was achieved by optimizing the combination of temperature and gas flows. The structural properties of graphene were studied using scanning electron microscopy, scanning confocal μ-Raman spectroscopy and optical microscopy. Evaluation of electric transport properties including contact resistance was carried out by transmission line method and four-probe method. The lowest contact resistance found was about at 350 Ωμm. In addition, different methods to transfer CVD graphene synthesized on copper were studied. Typical method using PMMA as a supporting layer leaves some residues after its removal, thus effecting on the performance of a graphene devices. In a metal assisted transfer method, metal is used as an interfacial layer between PMMA and graphene. This allows more effective removal of PMMA. However, Raman spectra of graphene transferred by metal assisted method showed somewhat lower quality than the PMMA assisted method

Spectroscopic Studies of III-V Semiconductor Materials for Improved Devices

Defects in semiconductor crystals and at their interfaces usually impair the properties and the performance of devices. These defects include, for example, vacancies (i.e., missing crystal atoms), interstitials (i.e., extra atoms between the host crystal sites), and impurities such as oxygen atoms. The defects can decrease (i) the rate of the radiative electron transition from the conduction band to the valence band, (ii) the amount of charge carriers, and (iii) the mobility of the electrons in the conduction band. It is a common situation that the presence of crystal defects can be readily concluded as a decrease in the luminescence intensity or in the current flow for example. However, the identification of the harmful defects is not straightforward at all because it is challenging to characterize local defects with atomic resolution and identification. Such atomic-scale knowledge is however essential to find methods for reducing the amount of defects in energy-efficient semiconductor devices. The defects formed in thin interface layers of semiconductors are particularly difficult to characterize due to their buried and amorphous structures. Characterization methods which are sensitive to defects often require well-defined samples with long range order. Photoelectron spectroscopy (PES) combined with photoluminescence (PL) or electrical measurements is a potential approach to elucidate the structure and defects of the interface. It is essential to combine the PES with complementary measurements of similar samples to relate the PES changes to changes in the interface defect density. Understanding of the nature of defects related to III-V materials is relevant to developing for example field-effect transistors which include a III-V channel, but research is still far from complete. In this thesis, PES measurements are utilized in studies of various III-V compound semiconductor materials. PES is combined with photoluminescence measurements to study the SiO2/GaAs, SiNx/GaAs and BaO/GaAs interfaces. Also the formation of novel materials InN and photoluminescent GaAs nanoparticles are studied. Finally, the formation of Ga interstitial defects in GaAsN is elucidated by combining calculational results with PES measurements.

A SOA-based Framework for Multi-Devices and Multi-Platform User Interfaces

This thesis reports investigations on applying the Service Oriented Architecture (SOA) approach in the engineering of multi-platform and multi-devices user interfaces. This study has three goals: (1) analyze the present frameworks for developing multi-platform and multi-devices applications, (2) extend the principles of SOA for implementing a multi-platform and multi-devices architectural framework (SOA-MDUI), (3) applying and validating the proposed framework in the context of a specific application. One of the problems addressed in this ongoing research is the large amount of combinations for possible implementations of applications on different types of devices. Usually it is necessary to take into account the operating system (OS), user interface (UI) including the appearance, programming language (PL) and architectural style (AS). Our proposed approach extended the principles of SOA using patterns-oriented design and model-driven engineering approaches. Synthesizing the present work done in these domains, this research built and tested an engineering framework linking Model-driven Architecture (MDA) and SOA approaches to developing of UI. This study advances general understanding of engineering, deploying and managing multi-platform and multi-devices user interfaces as a service.