114 resultados para Counting circuits.
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La música té el poder de fer moure persones de totes les cultures perquè utilitza els mateixos circuits neuronals que el moviment
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Disseny tant a nivell de hardware com de software d’un cap mòbil amb tecnologia led RGBW controlat pel protocol DMX512. Aquest projecte es limita al disseny i a la realització de tots els elements de software i hardware necessaris per crear un prototipus de cap mòbil que pugui ser controlat mitjançant el protocol DMX. Per tant, està encarat completament cap a la vessant electrònica i de programació sense fer referència als materials i elements constructius utilitzats o sobre el disseny i estètica del producte
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We present a new asymptotic formula for the maximum static voltage in a simplified model for on-chip power distribution networks of array bonded integrated circuits. In this model the voltage is the solution of a Poisson equation in an infinite planar domain whose boundary is an array of circular pads of radius ", and we deal with the singular limit Ɛ → 0 case. In comparison with approximations that appear in the electronic engineering literature, our formula is more complete since we have obtained terms up to order Ɛ15. A procedure will be presented to compute all the successive terms, which can be interpreted as using multipole solutions of equations involving spatial derivatives of functions. To deduce the formula we use the method of matched asymptotic expansions. Our results are completely analytical and we make an extensive use of special functions and of the Gauss constant G
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This bachelor's degree thesis deals with homomorphic public-key cryptography, or in other words cryptosystems with special addition properties. Such cryptosystems are widely used in real life situations, for instance to make electronic voting secure. In Chapter 1 a few basic algebra results and other key concepts are introduced. Chapters 2 and 3 contain the algorithms and properties of the two cryptosystems which are considered to be the best for e-voting: Paillier and Joye-Libert. The thesis is concluded in Chapter 4, by comparing running times of the two above-mentioned cryptosystems, in simulations of real-life e-voting systems, with up to tens of thousands of voters, and different levels of security. Through these simulations, we discern the situations where each of the two cryptosystems is preferable.
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Comentari sobre l'article publicat anteriorment pels mateixos autors: Vargas, M; Pallás, R; The seemingly paradoxical noise behaviour some active circuits. IEEE Transactions on Instrumentation and Measurement. 1994, vol. 43, núm. 5, p. 764-767
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This work describes a simulation tool being developed at UPC to predict the microwave nonlinear behavior of planar superconducting structures with very few restrictions on the geometry of the planar layout. The software is intended to be applicable to most structures used in planar HTS circuits, including line, patch, and quasi-lumped microstrip resonators. The tool combines Method of Moments (MoM) algorithms for general electromagnetic simulation with Harmonic Balance algorithms to take into account the nonlinearities in the HTS material. The Method of Moments code is based on discretization of the Electric Field Integral Equation in Rao, Wilton and Glisson Basis Functions. The multilayer dyadic Green's function is used with Sommerfeld integral formulation. The Harmonic Balance algorithm has been adapted to this application where the nonlinearity is distributed and where compatibility with the MoM algorithm is required. Tests of the algorithm in TM010 disk resonators agree with closed-form equations for both the fundamental and third-order intermodulation currents. Simulations of hairpin resonators show good qualitative agreement with previously published results, but it is found that a finer meshing would be necessary to get correct quantitative results. Possible improvements are suggested.
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Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays anda noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in thispaper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanismsand shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.
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Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.