Architektur für verteilte, fehlertolerante Sensor-Aktor-Systeme

Magdeburg, Univ., Fak. für Informatik, Diss., 2011

Komponentenorientierte Modellierung elektrischer Systeme in der Mechatronik

Object-oriented simulation, mechatronic systems, non-iterative algorithm, electric components, piezo-actuator, symbolic computation, Maple, Sparse-Tableau, Library of components

Forearm surface EMG signals recognition and muscoloskeletal system dynamics identification using intelligent computational methods

Biosignals processing, Biological Nonlinear and time-varying systems identification, Electomyograph signals recognition, Pattern classification, Fuzzy logic and neural networks methods

Entwurf und Implementierung rekonfigurierbarer Controller für mechatronische Systeme

Magdeburg, Univ., Fak. für Maschinenbau, Diss., 2008

Untersuchungen zu nutzerbezogenen und technischen Aspekten beim Langzeiteinsatz mobiler Augmented Reality Systeme in industriellen Anwendungen

Magdeburg, Univ., Fak. für Informatik, Diss., 2009

Port-Katheter-Systeme in der Gynäkologie : eine Langzeituntersuchung zu Komplikationen und Risikofaktoren, Patientenzufriedenheit und Spülintervallen

Magdeburg, Univ., Med. Fak., Diss., 2011

Entwicklung eines Geschäftsmodells für verteilte ERP-Systeme auf Basis von Web Services

Magdeburg, Univ., Fak. für Informatik, Diss., 2012

Variables Nanodatenmanagement für eingebettete Systeme

Magdeburg, Univ., Fak. für Informatik, Diss., 2012

Simulation gleitgelagerter Systeme in Mehrkörperprogrammen unter Berücksichtigung mechanischer und thermischer Deformationen

Magdeburg, Univ., Fak. für Maschinenbau, Diss., 2013

erweitertes Kameramodell : Methoden und Werkzeuge für die dynamische Kamerasteuerung in interaktiven Systemen

Camera model, intelligent camera, intelligent interactive systems, visual emphasis, cinematic techniques, camera planning

Datenreduktion und ihre Anwendungen in adaptiven mechanischen Systemen

Adaptive mechanische Systeme, Formkontrolle, Formadaption, Modal-Entwicklung, Karhunen-Loéve-EntƯwicklung, Modellreduktion

Hierarchische Ansätze zur Lösung komplexer hybrider Regelungsprobleme

Hierarchische Regelung, Hybride Systeme, Verhalten dynamischer Systeme

Modellierung von eigenschaftsverteilten Systemen der Feststoffverfahrenstechnik

Eigenschaftsverteilte Systeme, Feststoffverfahrenstechnik, Wirbelschicht, Populationsbilanzen, Bruchverhalten, Partikelbildung, Membranunterstützte Reaktionsführung

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.