16 resultados para Separation efficiency
em Martin Luther Universitat Halle Wittenberg, Germany
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Liquid separation efficiency, liquid penetration, modeling, arrays of temperature, distribution, fluidized bed, two-phase-nozzle
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2011
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Membrane reactor, reactive membrane separation, arrheotrope, azeotrope, dusty gas model, esterification, residue curve map, distillation, kinetics, singular point, bifurcation
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Reaction separation processes, reactive distillation, chromatographic reactor, equilibrium theory, nonlinear waves, process control, observer design, asymptoticaly exact input/output-linearization
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Serotonin, dopamine, parental separation, microdialysis, methylphenidate
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Software product line, variability, virtual separation, ifdef, preprocessor, cpp, annotative approaches, annotations
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2010
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2011
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012
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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013
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Magdeburg, Univ., Fak. für Wirtschaftswiss., Diss., 2013
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In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.
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In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.
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This article is devoted to the research of channel efficiency for IP-traffic transmission over Digital Power Line Carrier channels. The application of serial WAN connections and header compression as methods to increase channel efficiency is considered. According to the results of the research an effective solution for network traffic transmission in DPLC networks was proposed.
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2014