17 resultados para Multicommodity flow algorithms
em Martin Luther Universitat Halle Wittenberg, Germany
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Electrokinetic transport, electrochromatography, electroosmotic flow, electrophoresis, concentration polarization, fixed beds, monoliths, dynamic NMR microscopy, quantitative confocal laser scanning microscopy, mathematical modelling, numerical analysis
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Step flow growth, meandering instability, coarsening
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Magdeburg, Univ., Fak. für Mathematik, Habil.-Schr., 2006
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Analyte retention, analyte transport, axial dispersion, adsorption, charge-selectivity, concentration polarization, confocal laser scanning microscopy, donnan-exclusion, electrical double layer; electrochromatography; electrohydrodynamics, electrokinetic instability, electroosmosis; electroosmotic flow; electroosmotic mobility, electroosmotic perfusion, electrophoresis, hierarchical porous media, hydrodynamic flow, induced-charge electroosmosis, ion-permselectivity, ion-permselective transport, monolith, nonequilibrium electrical double layer, nonequilibrium electrokinetic effects, nonlinear electroosmosis, plate height, plate number, porous media, pore-scale dispersion, refractive index matching, space charge effects, sphere packing, quantitative imaging, wall effect, zeta-potential
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Cross-Flow, Radial Jets Mixing, Temperature Homogenization, Optimization, Combustion Chamber, CFD
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Magdeburg, Univ., Fak. für Informatik, Diss., 2009
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2009
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2010
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2012
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This work describes a test tool that allows to make performance tests of different end-to-end available bandwidth estimation algorithms along with their different implementations. The goal of such tests is to find the best-performing algorithm and its implementation and use it in congestion control mechanism for high-performance reliable transport protocols. The main idea of this paper is to describe the options which provide available bandwidth estimation mechanism for highspeed data transport protocols and to develop basic functionality of such test tool with which it will be possible to manage entities of test application on all involved testing hosts, aided by some middleware.
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2013
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Magdeburg, Univ., Fak. für Informatik, Diss., 2013
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In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.
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In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.
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Some practical aspects of Genetic algorithms’ implementation regarding to life cycle management of electrotechnical equipment are considered.