17 resultados para Magnetic memory.

em Martin Luther Universitat Halle Wittenberg, Germany


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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2012

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Magdeburg, Univ., Fak. für Mathematik, Diss., 2006

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Performance monitoring, ERN, CRN, Pe, Memory, Llist learning, Emotion, IAPS, N2, Reinforcement Learning Hypothesis, Conflict Monitoring Hypothesis

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Independent Component Analysis, Time Series Analysis, Functional Magnetic Resonance Imaging

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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2009

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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2012

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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013

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Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2013

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Magdeburg, Univ., Med. Fak., Diss., 2014

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Aus: Soft matter, Vol. 10.2014, H. 25, S. 4487 - 4497

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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2014

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The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

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Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

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Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2015