Automatisierte Hardware-Software Partitionierung am Beispiel eines eingebetteten, echtzeitfähigen Stereobildanalysesystems in Kraftfahrzeugen

Hardware-Software Co-Design, Simulated Annealing, Real-Time Image Processing, Automated Hardware-Software Partitioning

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Modeling, design, and optimization of radiofrequency micromechanical structures

Coupled Electromechanical Analysis, MEMS Modeling, MEMS, RF MEMS Switches, Defected Ground Structures, Reconfigurable Resonator

Implementation of a unified userspace time handling library under the Linux OS

An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% (busy-wait) to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.

Entwicklung eines QAM-Modulators mit variabler Ausgangsfrequenz

Die Aufgabe bestand in der Entwicklung eines QAM-Modulators mit variabler Ausgangsfrequenz, wie er in DVB-C verwendet wird. Als Hardware-Plattform wurden eine FPGA von der Firma Altera und der AD9857 von der Firma Analog Devices ausgewählt. Mit dem AD9857 wurden die Interpolationsfilterung, die Quadraturmodulation und die D/A-Wandlung umgesetzt. Mit dem FPGA wurden die Transportströme erzeugt, sowie die Kanalcodierung, die Symbolverarbeitung, das digitale Basisbandfilter und die Steuerung des AD9857 realisiert. Die Software wurde mit Quartus II, ModelSim von Altera und Verilog HDL erstellt.

Entwicklung der Nachrüstlösung einer Brandmeldeanlage zur Anbindung und Visualisierung an das KNX System

Diese Arbeit beschreibt die Nachrüstlösung einer Brandmeldeanlage der Firma Notifier zur Anbindung und Visualisierung an das KNX System. Die Anbindung soll ermöglichen, dass Informationen der Brandmeldeanlage in Form von Feuer- und Statusmeldungen an dem KNX-Bus übertragen und visualisiert werden können. Die positiven Effekte, die daraus resultieren, sind zum einen die mögliche Verknüpfung mit anderen Teilnehmern im KNX-System und zum anderen die daraus resultierende Möglichkeit, alle vorhandenen Systeme in einem Gebäude visualisiert darstellen zu können. Nach der Recherche, zu dem von dem Systemen verwendeten Schnittstellen und Kommunikationsmöglichkeiten, wurde die Auswahl der benötigten Bauteile getroffen, um die Anbindung der beiden Systeme zu ermöglichen. Die daraus resultierende Verwendung eines Mikrocontrollers erforderte die Entwicklung und Programmierung dessen Software. Anschließend war es möglich durch hardware- und softwaretechnischen Lösungen eine Anbindung der beiden Systeme zu ermöglichen und das daraus gesteckte Ziel, eine Visualisierung durch Verwendung spezieller Software des KNX, zu erreichen.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.