11 resultados para French contemporary novel
em Martin Luther Universitat Halle Wittenberg, Germany
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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2012
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Protease-activated receptor; c-Jun N-terminal kinase (JNK); thrombin; neuroprotection; siRNA
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Gastrointestinal cancers, HCC, ectopeptidases, differential display, gasdermin-like
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DAPK, Apoptosis, p38, macrophages, survival
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2010
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Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2010
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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013
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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013
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This work is dedicated to comparison of open source as well as proprietary transport protocols for highspeed data transmission via IP networks. The contemporary common TCP needs significant improvement since it was developed as general-purpose transport protocol and firstly introduced four decades ago. In nowadays networks, TCP fits not all communication needs that society has. Caused of it another transport protocols have been developed and successfully used for e.g. Big Data movement. In scope of this research the following protocols have been investigated for its efficiency on 10Gbps links: UDT, RBUDP, MTP and RWTP. The protocols were tested under different impairments such as Round Trip Time up to 400 ms and packet losses up to 2%. Investigated parameters are the data rate under different conditions of the network, the CPU load by sender andreceiver during the experiments, size of feedback data, CPU usage per Gbps and the amount of feedback data per GiByte of effectively transmitted data. The best performance and fair resources consumption was observed by RWTP. From the opensource projects, the best behavior is showed by RBUDP.
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The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.
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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2015