Experimental investigation of heat transfer characteristics from arrays of free impinging circular jets and hole channels

Free Tube Jet - Impingemenet - Heat Transfer - Arrary - Infrared Techuique - Hole Channels - Heat Transfer Uniformaty

CD95-induced apoptosis in health and disease dimers at the DISC and the effect of c-FLIP R on L. Monocytogenes infection

Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013

apoptosis-regulator c-FLIP : functional role in urothelial carcinoma and autoimmunity and identification of novel CD95 DISC-interacting proteins

Magdeburg, Univ., Fak. für Naturwiss., Diss., 2013

On utilising change over time in data mining

Magdeburg, Univ., Fak. für Informatik, Diss., 2013

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Assessment of the VoIP Transmission Quality over Digital Power Line Carrier Channels

This article is devoted to the research of VoIP transmission quality over Digital Power Line Carrier channels. Assessment of quality transmission is performed using E-model. Paper considers the possibility of joint using of Digital Power Line carrier equipment with different architecture in one network. As a result of the research, the rule for constructing of multi-segment Digital Power Line Carrier channels was formulated. This rule allows minimizing the transmission delay and saving frequency resources of high voltage Power Line Carrier range.

The Research of Increase of Channel Efficiency for IP Traffic Transmission over Digital Power Line Carrier Channels

This article is devoted to the research of channel efficiency for IP-traffic transmission over Digital Power Line Carrier channels. The application of serial WAN connections and header compression as methods to increase channel efficiency is considered. According to the results of the research an effective solution for network traffic transmission in DPLC networks was proposed.

Mapping of the healthy immunoglobulin repertoire over the course of B cell maturation by deep pyrosequencing

Healthy immunoglobulin repertoire has not been extensively evaluated reflecting in part the challenge of generating sufficiently robust data sets by conventional clonal sequencing. Deep sequencing has revolutionized the capacity to evaluate the depth and breadth of the Ig repertoire along the B cell developmental pathway, and can be used to pin point defect(s) of primary or acquired B-cell associated diseases. In this study healthy IgM and IgG repertoires were studied by 454-pyrosequencing to establish the healthy controls for diseased repertoires. (...)

Understanding and monitoring attitudes of product properties over time

Magdeburg, Univ., Fak. für Informatik, Diss., 2015

Episodes of the life and death of thin fluid membranes : patterns and dynamics at the cross-over from two to three dimensions

Otto-von Guericke-Universität Magdeburg, Fakultät für Naturwissenschaften, Dissertation, 2016