Verfahren zur direkten Implementierung von Algorithmen auf Gatterebene

Bit serial, processing, digital signal processing, transmission, time division, linear programming, linear optimization

Neural correlates of target detection in the attentional blink

Attention, attentional blink, rapid serial visual presentation, RSVP, ERP, EEG, fMRI, gammaband, oscillatiory activity

Ansteuerkonzept für piezoelektrische Aktoren

Piezoelectric actuator, electric drive, switching amplifier, charge pump, energy recovery, model of the piezoelectric actuator, mixed-mode-simulation, FPGA, voltage control, bit serial implementation

Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

The Research of Increase of Channel Efficiency for IP Traffic Transmission over Digital Power Line Carrier Channels

This article is devoted to the research of channel efficiency for IP-traffic transmission over Digital Power Line Carrier channels. The application of serial WAN connections and header compression as methods to increase channel efficiency is considered. According to the results of the research an effective solution for network traffic transmission in DPLC networks was proposed.