monitoring-based approach to object-oriented real-time computing

Monitoring, object-orientation, real-time, execution-time, scheduling

Design and development of high gain wideband microstrip antenna and DGS filters using numerical experimentation approach

Microstrip antenna, Wideband antennas, high gain antennas, Microstrip filters, DGS filters , low-pass filter, band-pass filter

imaging capabilities of ground penetrating radar for the detection of buries anti-personnel landmines

Subsurface Radar, Ground Penetrating Radar (GPR), Synthetic Aperture Radar (SAR), Anti-Personnel Landmine, Antenna Desing, Field Simulation, Focusing, Dielectric Lens, Geophysics, Soil Properties

Numerical investigation of micro and macro mechanical behaviour of granular media via a discrete element approach

Magdeburg, Univ., Fak. für Mathematik, Diss., 2009

Simultaneous recording of EEG and fMRI : new approach to remove gradient and ballistocardiogram EEG-artifacts

Magdeburg, Univ., Fak. für Naturwiss., Diss., 2009

Advanced production systems : developing context-oriented method and adaptation capabilities for enhanced supply network

Magdeburg, Univ., Fak. für Maschinenbau, Diss., 2014

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

power network concept : a theoretical and empirical approach to strategy in the global network economy

Magdeburg, Univ., Fak. für Wirtschaftswiss., Diss., 2014

Dynamics in growth and metabolism of adherent MDCK cells unraveled by an integrated modeling approach

Otto-von-Guericke-Universität Magdeburg, Fakultät für Verfahrens- und Systemtechnik, Univ., Dissertation, 2015