Design and control of combined chemical processes for the production of pure enantiomers

Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2013

Collaboration process design for ideation in distributed environments : approaches to support collaborative ideation in global virtual groups using technological support

Magdeburg, Univ., Fak. für Informatik, Diss., 2012

Granular flow and design studies in flighted rotating drums

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2013

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware : Implementations,Parallelization Prospectsand Possible Improvements

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniquesfor maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables,and an approach for performing parallel addition of N input symbols.

Optimal design in the presence of random or fixed block effects

Magdeburg, Univ., Fak. für Mathematik, Diss., 2014

Optimal experimental design for parameter identification and model selection

Magdeburg, Univ., Fak. für Elektrotechnik und Informationstechnik, Diss., 2014

Process design based on CO 2-expanded liquids as solvents

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2014

Design, modeling and control of an autonomous field robot for white asparagus harvesting

Magdeburg, Univ., Fak. für Maschinenbau, Diss., 2014

Die Vermittlung des heimlichen Lehrplans im Klassenraum : - Beobachtungen zu genderspezifischen Interaktionen mittels experimentellem Design

Der heimliche Lehrplan beschreibt soziale Werte, Normen und Regeln, welcher als Sozialisationsprozess den Schulalltag beeinflusst. Die eigens für die Thesis erstellten Hypothesen fragen nach der Validität der Methode sowie genderspezifischen Interaktionen. Schwerpunkt dieser Bachelor-Thesis sind Beobachtungen in zwei Sekundarschulen. Das Untersuchungsdesign ist experimentell an den Erhebungsbogen von zwei amerikanischen Wissenschaftlerinnen aus dem Jahr 1993 angelehnt. Nach einer Pretestphase sowie Modifizierungsprozess wurde das gewonnene Material quantitativ mithilfe des SPSS-Programms und qualitativ durch die Inhaltsanalyse aufbereitet und ausgewertet. Die Hypothesen werden durch die Auswertung und mithilfe von Gütekriterien beantwortet, sodass die Methodenvalidität größtenteils belegt werden kann. Tendenzen für geschlechterspezifische Interaktionen sind erkennbar, allerdings schwer zu generalisieren. Im Fazit wird die Bedeutung des heimlichen Lehrplans sowie die Geschlechtergerechtigkeit in Schulen diskutiert.

Flow design optimization of blood pumps considering hemolysis

Magdeburg, Univ., Fak. für Verfahrens- und Systemtechnik, Diss., 2015

Design of biped robot walking with double-support phase

Otto-von-Guericke-Universität Magdeburg, Fakultät für Maschinenbau, Univ., Dissertation, 2015