Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software phantoms in medical image analysis

Magdeburg, Univ., Fak. für Informatik, Diss., 2015

Entwicklung einer benutzerfreundlichen Software zur Berechnung von Rundfunk-Sendeantennen

Die Abteilung Sendertechnik des Norddeutschen Rundfunks betreibt die Sender zur Versorgung der Rundfunknutzer und befasst sich unter anderem mit der Planung und Optimierung von Sendeantennen. Das Ziel dieser Bachelorarbeit war die Entwicklung einer Software, mit der Horizontaldiagramme von Antennen erstellt, angepasst und dokumentiert werden können. Dafür wurde eine vorhandene LabVIEW-Software in ihren Grundzügen übernommen, in eine neue, in Java entwickelte Programmumgebung übertragen und dort erweitert und optimiert. Die Arbeit dokumentiert die Grundlagen der Sendeantennenplanung und die programmiertechnischen Entwicklungsschritte bis hin zur fertiggestellten und funktionsfähigen Software. Im Speziellen geht sie dabei auf die Berechnung von Antennensystemen, die Erstellung von Horizontaldiagrammen sowie die objektorientierte Programmierung und die Erstellung von grafischen Benutzeroberflächen ein. Dabei werden die einzelnen Entwicklungsschritte dokumentiert und erläutert sowie die Validierung der Software beschrieben.