Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

IEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science)

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Interoperability on low power devices

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

Design of future distribution grids

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Switching mode power amplifier for bluetooth applications

Modern fully integrated transceivers architectures, require circuits with low area, low cost, low power, and high efficiency. A key block in modern transceivers is the power amplifier, which is deeply studied in this thesis. First, we study the implementation of a classical Class-A amplifier, describing the basic operation of an RF power amplifier, and analysing the influence of the real models of the reactive components in its operation. Secondly, the Class-E amplifier is deeply studied. The different types of implementations are reviewed and theoretical equations are derived and compared with simulations. There were selected four modes of operation for the Class-E amplifier, in order to perform the implementation of the output stage, and the subsequent comparison of results. This led to the selection of the mode with the best trade-off between efficiency and harmonics distortion, lower power consumption and higher output power. The optimal choice was a parallel circuit containing an inductor with a finite value. To complete the implementation of the PA in switching mode, a driver was implemented. The final block (output stage together with the driver) got 20 % total efficiency (PAE) transmitting 8 dBm output power to a 50 W load with a total harmonic distortion (THD) of 3 % and a total consumption of 28 mW. All implementations are designed using standard 130 nm CMOS technology. The operating frequency is 2.4 GHz and it was considered an 1.2 V DC power supply. The proposed circuit is intended to be used in a Bluetooth transmitter, however, it has a wider range of applications.

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW

Frequency-domain receiver design for doubly-selective channels

This work is devoted to the broadband wireless transmission techniques, which are serious candidates to be implemented in future broadband wireless and cellular systems, aiming at providing high and reliable data transmission and concomitantly high mobility. In order to cope with doubly-selective channels, receiver structures based on OFDM and SC-FDE block transmission techniques, are proposed, which allow cost-effective implementations, using FFT-based signal processing. The first subject to be addressed is the impact of the number of multipath components, and the diversity order, on the asymptotic performance of OFDM and SC-FDE, in uncoded and for different channel coding schemes. The obtained results show that the number of relevant separable multipath components is a key element that influences the performance of OFDM and SC-FDE schemes. Then, the improved estimation and detection performance of OFDM-based broadcasting systems, is introduced employing SFN (Single Frequency Network) operation. An initial coarse channel is obtained with resort to low-power training sequences estimation, and an iterative receiver with joint detection and channel estimation is presented. The achieved results have shown very good performance, close to that with perfect channel estimation. The next topic is related to SFN systems, devoting special attention to time-distortion effects inherent to these networks. Typically, the SFN broadcast wireless systems employ OFDM schemes to cope with severely time-dispersive channels. However, frequency errors, due to CFO, compromises the orthogonality between subcarriers. As an alternative approach, the possibility of using SC-FDE schemes (characterized by reduced envelope fluctuations and higher robustness to carrier frequency errors) is evaluated, and a technique, employing joint CFO estimation and compensation over the severe time-distortion effects, is proposed. Finally, broadband mobile wireless systems, in which the relative motion between the transmitter and receiver induces Doppler shift which is different or each propagation path, is considered, depending on the angle of incidence of that path in relation to the direction of travel. This represents a severe impairment in wireless digital communications systems, since that multipath propagation combined with the Doppler effects, lead to drastic and unpredictable fluctuations of the envelope of the received signal, severely affecting the detection performance. The channel variations due this effect are very difficult to estimate and compensate. In this work we propose a set of SC-FDE iterative receivers implementing efficient estimation and tracking techniques. The performance results show that the proposed receivers have very good performance, even in the presence of significant Doppler spread between the different groups of multipath components.

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

A random access MAC protocol for MPR satellite networks

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Multipacket reception in LTE femtocell networks

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores