An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Monitorização integrada para sistemas de alimentação distribuídos

Mestrado em Engenharia Electrotécnica e de Computadores

Aplicação web para tratamento estatístico de dados de teste

Mestrado em Engenharia Electrotécnica e de Computadores

JamLab: augmenting sensornet testbeds with realistic and controlled interference generation

Radio interference drastically affects the performance of sensor-net communications, leading to packet loss and reduced energy-efficiency. As an increasing number of wireless devices operates on the same ISM frequencies, there is a strong need for understanding and debugging the performance of existing sensornet protocols under interference. Doing so requires a low-cost flexible testbed infrastructure that allows the repeatable generation of a wide range of interference patterns. Unfortunately, to date, existing sensornet testbeds lack such capabilities, and do not permit to study easily the coexistence problems between devices sharing the same frequencies. This paper addresses the current lack of such an infrastructure by using off-the-shelf sensor motes to record and playback interference patterns as well as to generate customizable and repeat-able interference in real-time. We propose and develop JamLab: a low-cost infrastructure to augment existing sensornet testbeds with accurate interference generation while limiting the overhead to a simple upload of the appropriate software. We explain how we tackle the hardware limitations and get an accurate measurement and regeneration of interference, and we experimentally evaluate the accuracy of JamLab with respect to time, space, and intensity. We further use JamLab to characterize the impact of interference on sensornet MAC protocols.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1)

Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e Sistemas

Sistema de apoio à racionalização da utilização de energia eléctrica

Esta dissertação descreve o sistema de apoio à racionalização da utilização de energia eléctrica desenvolvido no âmbito da unidade curricular de Tese/Dissertação. O domínio de aplicação enquadra-se no contexto da Directiva da União Europeia 2006/32/EC que declara ser necessário colocar à disposição dos consumidores a informação e os meios que promovam a redução do consumo e o aumento da eficiência energética individual. O objectivo é o desenvolvimento de uma solução que permita a representação gráfica do consumo/produção, a definição de tectos de consumo, a geração automática de alertas e alarmes, a comparação anónima com clientes com perfil idêntico por região e a previsão de consumo/produção no caso de clientes industriais. Trata-se de um sistema distribuído composto por front-end e back-end. O front-end é composto pelas aplicações de interface com o utilizador desenvolvidas para dispositivos móveis Android e navegadores Web. O back-end efectua o armazenamento e processamento de informação e encontra-se alojado numa plataforma de cloud computing – o Google App Engine – que disponibiliza uma interface padrão do tipo serviço Web. Esta opção assegura interoperabilidade, escalabilidade e robustez ao sistema. Descreve-se em detalhe a concepção, desenvolvimento e teste do protótipo realizado, incluindo: (i) as funcionalidades de gestão e análise de consumo e produção de energia implementadas; (ii) as estruturas de dados; (iii) a base de dados e o serviço Web; e (iv) os testes e a depuração efectuados. (iv) Por fim, apresenta-se o balanço deste projecto e efectuam-se sugestões de melhoria.

Using Quicktrace to collect runtime execution traces easily and automatically

IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 4, Dec, 2015. U.S.A.

Sistema aplicacional para o acompanhamento e monitorização de casos de perturbação psicótica

Pretende-se, na presente dissertação, descrever o trabalho desenvolvido e os conhecimentos adquiridos no decorrer do projeto “iCOPE”, realizado no âmbito do curso de Mestrado em Engenharia de Computação e Instrumentação Médica. O projeto consistiu no desenvolvimento de um sistema aplicacional para o auxílio à prestação de serviços e cuidados de saúde a pacientes com doenças psicóticas tanto através de ferramentas de autogestão, como por funcionalidades que permitirão a um terapeuta monitorizar as ocorrências comunicadas pelos respetivos pacientes atribuídos. As tarefas à responsabilidade do autor desta dissertação compreenderam o levantamento e especificação de requisitos funcionais, o desenvolvimento das funcionalidades e interfaces de gestão de utilizadores e administração do sistema, o desenvolvimento das funcionalidades e interfaces para utilização pelos terapeutas e a criação de ferramentas para a instalação do servidor aplicacional central, existindo ainda cooperação no desenvolvimento de funcionalidades e interfaces para utilização pelos pacientes, nomeadamente ao nível da modelização da base de dados e na realização de testes e deteção de erros. Os resultados da avaliação das interfaces desenvolvidas, obtidos por meio da análise de respostas dadas por um grupo de potenciais utilizadores a um inquérito de usabilidade anónimo, demonstraram que estes estão satisfeitos com a solução implementada, havendo, no entanto, margem para futuros melhoramentos e incremento de funcionalidades.