Creating shared value – a nova abordagem estratégica de Responsabilidade social empresarial

Dissertação de Mestrado apresentada ao Instituto Supeior de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Marketing Digital, sob a orientação da Doutora Sandrina Francisca Teixeira

E-Learning as a shared service in shared services centers

Book Subtitle International Conference, CENTERIS 2010, Viana do Castelo, Portugal, October 20-22, 2010, Proceedings, Part II

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

Shared resources and precedence constraints with capacity sharing and stealing

This paper proposes a new strategy to integrate shared resources and precedence constraints among real-time tasks, assuming no precise information on critical sections and computation times is available. The concept of bandwidth inheritance is combined with a greedy capacity sharing and stealing policy to efficiently exchange bandwidth among tasks, minimising the degree of deviation from the ideal system's behaviour caused by inter-application blocking. The proposed capacity exchange protocol (CXP) focus on exchanging extra capacities as early, and not necessarily as fairly, as possible. This loss of optimality is worth the reduced complexity as the protocol's behaviour nevertheless tends to be fair in the long run and outperforms other solutions in highly dynamic scenarios, as demonstrated by extensive simulations.

Mode III interlaminar fracture of carbon/epoxy laminates using the edge crack torsion (ECT) test

The mode III interlaminar fracture of carbon/epoxy laminates was evaluated with the edge crack torsion (ECT) test. Three-dimensional finite element analyses were performed in order to select two specimen geometries and an experimental data reduction scheme. Test results showed considerable non-linearity before the maximum load point and a significant R-curve effect. These features prevented an accurate definition of the initiation point. Nevertheless, analyses of non-linearity zones showed two likely initiation points corresponding to GIIIc values between 850 and 1100 J/m2 for both specimen geometries. Although any of these values is realistic, the range is too broad, thus showing the limitations of the ECT test and the need for further research.