Towards network-on-chip agreement protocols

Demands for functionality enhancements, cost reductions and power savings clearly suggest the introduction of multiand many-core platforms in real-time embedded systems. However, when compared to uni-core platforms, the manycores experience additional problems, namely the lack of scalable coherence mechanisms and the necessity to perform migrations. These problems have to be addressed before such systems can be considered for integration into the realtime embedded domain. We have devised several agreement protocols which solve some of the aforementioned issues. The protocols allow the applications to plan and organise their future executions both temporally and spatially (i.e. when and where the next job will be executed). Decisions can be driven by several factors, e.g. load balancing, energy savings and thermal issues. All presented protocols are analytically described, with the particular emphasis on their respective real-time behaviours and worst-case performance. The underlying assumptions are based on the multi-kernel model and the message-passing paradigm, which constitutes the communication between the interacting instances.

Integration of TCP/IP and PROFIBUS protocols

Recent technological developments are pulling fieldbus networks to support a new wide class of applications, such as industrial multimedia applications. These applications are usually supported by the widely used TCP/IP stack. It is thus essential to provide support to TCP/IP based applications, in fieldbus networks. This paper presents an effort that is being carried out to integrate the TCP/IP and PROFIBUS stacks, in order to support industrial multimedia applications, whilst guarantying the timing requirements of control-related traffic.

Supporting internet protocols in master-slave fieldbus networks

In this paper we describe how to integrate Internet Protocols (IP) into a typical hierarchical master-slave fieldbus network, supporting a logical ring token passing mechanism between master stations. The integration of the TCP/IP protocols in the fieldbus protocol rises a number of issues that must be addressed properly. In this paper we particularly address the issues related to the conveyance of IP fragments in fieldbus frames (fragmentation/de-fragmentation) and on how to support the symmetry inherent to the TCP/IP protocols in fieldbus slaves, which lack communication initiative.

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).

Two protocols without periodicity for the global and preemptive scheduling problem of multi-mode real-time systems upon multiprocessor Platforms

We consider the problem of scheduling a multi-mode real-time system upon identical multiprocessor platforms. Since it is a multi-mode system, the system can change from one mode to another such that the current task set is replaced with a new task set. Ensuring that deadlines are met requires not only that a schedulability test is performed on tasks in each mode but also that (i) a protocol for transitioning from one mode to another is specified and (ii) a schedulability test for each transition is performed. We propose two protocols which ensure that all the expected requirements are met during every transition between every pair of operating modes of the system. Moreover, we prove the correctness of our proposed algorithms by extending the theory about the makespan determination problem.

Highly scalable aggregate computations in cyber-physical systems: physical environment meets communication protocols

In this paper, we focus on large-scale and dense Cyber- Physical Systems, and discuss methods that tightly integrate communication and computing with the underlying physical environment. We present Physical Dynamic Priority Dominance ((PD)2) protocol that exemplifies a key mechanism to devise low time-complexity communication protocols for large-scale networked sensor systems. We show that using this mechanism, one can compute aggregate quantities such as the maximum or minimum of sensor readings in a time-complexity that is equivalent to essentially one message exchange. We also illustrate the use of this mechanism in a more complex task of computing the interpolation of smooth as well as non-smooth sensor data in very low timecomplexity.

Multi-Objective and Financial Portfolio Optimization of Carrier-Sense Multiple Access Protocols with Cooperative Diversity

8th International Workshop on Multiple Access Communications (MACOM2015), Helsinki, Finland.

Energy-efficient MAC protocols for WBANs: Opportunities and challenges

Wireless body area networks (WBANs) are expected to play a significant role in smart healthcare systems. One of the most important attributes of WBANs is to increase network lifetime by introducing novel and low-power techniques on the energy-constrained sensor nodes. Medium access control (MAC) protocols play a significant role in determining the energy consumption in WBANs. Existing MAC protocols are unable to accommodate communication requirements in WBANs. There is a need to develop novel, scalable and reliable MAC protocols that must be able to address all these requirements in a reliable manner. In this special issue, we attracted high quality research and review papers on the recent advances in MAC protocols for WBANs.