5 resultados para VeriStand, Custom devices, Hardware in the loop, LabView, FPGA, ECU
em Instituto Politécnico do Porto, Portugal
Resumo:
For the past years wireless sensor networks (WSNs) have been coined as one of the most promising technologies for supporting a wide range of applications. However, outside the research community, few are the people who know what they are and what they can offer. Even fewer are the ones that have seen these networks used in real world applications. The main obstacle for the proliferation of these networks is energy, or the lack of it. Even though renewable energy sources are always present in the networks environment, designing devices that can efficiently scavenge that energy in order to sustain the operation of these networks is still an open challenge. Energy scavenging, along with energy efficiency and energy conservation, are the current available means to sustain the operation of these networks, and can all be framed within the broader concept of “Energetic Sustainability”. A comprehensive study of the several issues related to the energetic sustainability of WSNs is presented in this thesis, with a special focus in today’s applicable energy harvesting techniques and devices, and in the energy consumption of commercially available WSN hardware platforms. This work allows the understanding of the different energy concepts involving WSNs and the evaluation of the presented energy harvesting techniques for sustaining wireless sensor nodes. This survey is supported by a novel experimental analysis of the energy consumption of the most widespread commercially available WSN hardware platforms.
Resumo:
The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.
Resumo:
6th Graduate Student Symposium on Molecular Imprinting
Resumo:
Poster presented in Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.
Resumo:
Presented at Work in Progress Session, The 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2015). 24 to 27, Mar, 2015. Porto, Portugal.