O uso do smartphone na avaliação da dorsiflexão da tibiotársica, do passo rápido anterior/lateral/posterior e da marcha em idosos

Introdução: A correta avaliação das capacidades do idoso será fundamental na diminuição do risco de queda inerente ao envelhecimento. Os Smartphones são uma boa ferramenta para a avaliação das capacidades em idosos. Objetivo: Verificar se o smartphone é uma ferramenta de avaliação do ângulo de dorsiflexão ativa da tibiotársica (Dors. TT) e em diferentes parâmetros relacionados com a marcha. ; Métodos: Estudo transversal correlacional, com amostra composta por 27 indivíduos com mais de 60 anos. Procedeu-se à recolha de dados através de um sistema de análise cinemática em 3D com conexão a uma plataforma de forças e de uma aplicação para Smartphone (Fraunhofer®, Porto, Portugal), de forma a verificar a funcionalidade desta última. As variáveis medidas foram a Dors. TT; e todas a variáveis relacionadas com a marcha. Resultados: A dors. TT apresentou uma correlação forte positiva (rs=0,8; p<0,001) entre os dados dos dois instrumentos, assim como no balanço pélvico (rp=0,8; p<0,001), na velocidade na marcha (rp=0,7; p<0,001) e no nº de passos posteriores (rs=0,8; p<0,001). Observou-se uma correlação moderada positiva na duração do passo direito, na duração do passo, na duração da passada, na cadência, no comprimento do passo esq., no comprimento do passo e no deslocamento lateral da pélvis (rp=0,6; p≤0.008). Na percentagem da fase de apoio (%FA) (rs =-0.6; p= 0.007) e na medição da cadência lateral (rs =-0.4; p= 0.042) observou-se uma correlação moderada negativa e na cad. post. (rs=-0,7; p<0,001) uma correlação forte negativa. Conclusão: A aplicação para Smartphone parece ser uma ferramenta útil para avaliar corretamente o ângulo de dorsiflexão da tibiotársica, a contagem do número de passos no sentido posterior, o balanço pélvico e a velocidade. Contudo, necessita ser reajustada para as outras variáveis.

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Controller implementation using analog reconfigurable hardware (FPAA)

This Thesis has the main target to make a research about FPAA/dpASPs devices and technologies applied to control systems. These devices provide easy way to emulate analog circuits that can be reconfigurable by programming tools from manufactures and in case of dpASPs are able to be dynamically reconfigurable on the fly. It is described different kinds of technologies commercially available and also academic projects from researcher groups. These technologies are very recent and are in ramp up development to achieve a level of flexibility and integration to penetrate more easily the market. As occurs with CPLD/FPGAs, the FPAA/dpASPs technologies have the target to increase the productivity, reducing the development time and make easier future hardware reconfigurations reducing the costs. FPAA/dpAsps still have some limitations comparing with the classic analog circuits due to lower working frequencies and emulation of complex circuits that require more components inside the integrated circuit. However, they have great advantages in sensor signal condition, filter circuits and control systems. This thesis focuses practical implementations of these technologies to control system PID controllers. The result of the experiments confirms the efficacy of FPAA/dpASPs on signal condition and control systems.