Fractional-order impulse response of the respiratory system

This paper presents the measurement, frequency-response modeling and identification, and the corresponding impulse time response of the human respiratory impedance and admittance. The investigated adult patient groups were healthy, diagnosed with chronic obstructive pulmonary disease and kyphoscoliosis, respectively. The investigated children patient groups were healthy, diagnosed with asthma and cystic fibrosis, respectively. Fractional order (FO) models are identified on the measured impedance to quantify the respiratory mechanical properties. Two methods are presented for obtaining and simulating the time-domain impulse response from FO models of the respiratory admittance: (i) the classical pole-zero interpolation proposed by Oustaloup in the early 90s, and (ii) the inverse discrete Fourier Transform (DFT). The results of the identified FO models for the respiratory admittance are presented by means of their average values for each group of patients. Consequently, the impulse time response calculated from the frequency response of the averaged FO models is given by means of the two methods mentioned above. Our results indicate that both methods provide similar impulse response data. However, we suggest that the inverse DFT is a more suitable alternative to the high order transfer functions obtained using the classical Oustaloup filter. Additionally, a power law model is fitted on the impulse response data, emphasizing the intrinsic fractal dynamics of the respiratory system.

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.