Electronic Redesign of an Industrial Lift

This project, realized at the company ABER Ltd, describes the process followed for the developing of an electronic control system for a hydraulic elevator. The previous control system was based on relay logic, and the company wanted to change it to a microcontroller based technology. To do so, different approaches were studied and finally the selected technology for the development was the Raspberry Pi. After, the software needed for all the elevator types was developed, and the interface hardware was selected. In the end, several test were made to adjust the software and the hardware and to prove the good operation of the system.

Improving the reliability of WiDom in a single broadcast domain

WiDom is a previously proposed prioritized medium access control protocol for wireless channels. We present a modification to this protocol in order to improve its reliability. This modification has similarities with cooperative relaying schemes, but, in our protocol, all nodes can relay a carrier wave. The preliminary evaluation shows that, under transmission errors, a significant reduction on the number of failed tournaments can be achieved.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

Estudo e Coordenação das Principais Protecções Eléctricas de Geradores e Transformadores de uma Central de Cogeração

O Sector eléctrico possui uma grande importância nas sociedades modernas. Dados os elevados custos de produção de energia e o grande impacto que esta tem na nossa economia e na sociedade, em geral, a utilização mais eficiente da energia é um factor fulcral. Com a evolução da electrónica e consequente aumento das capacidades dos computadores, as protecções eléctricas são cada vez mais eficazes e com índices de fiabilidade mais elevados, algo muito importante em instalações de elevado custo de investimento e manutenção. No entanto, o seu bom funcionamento está dependente do correcto dimensionamento das protecções e de uma análise técnica capaz de prever necessidades futuras. Após uma breve introdução no capítulo 1 é efectuado no capítulo 2 um breve estudo de protecções eléctricas e o seu estado de arte. Nos Capítulos 3 e 4 é efectuado o dimensionamento e estudo da selectividade das protecções de grupo de Alternador e Transformador escolhidos para a nova central de cogeração da refinaria de Matosinhos da Galp. No presente estudo foram apenas consideradas as protecções típicas de alternador e apenas a protecção diferencial do transformador. Todas as protecções foram dimensionadas com base no tutorial de protecções de geradores do IEE e com informação referente ao manual de instruções do relé G60 da GE industrial systems, o DTP-B da GE multilin e o ELIN Power Plant Automation. No Capítulo 5 é demonstrada a importância da análise Safety Instruments Systems (SIS), o seu modo de aplicação e necessidade de implementação em locais industriais como o caso em estudo. Por último, é efectuado um pequeno estudo económico onde é efectuada a comparação dos custos dos diversos equipamentos, protecções e manutenções efectuadas.