Scalable and Efficient Configuration of TimeDivision Multiplexed Resources

Consumer-electronics systems are becoming increasingly complex as the number of integrated applications is growing. Some of these applications have real-time requirements, while other non-real-time applications only require good average performance. For cost-efficient design, contemporary platforms feature an increasing number of cores that share resources, such as memories and interconnects. However, resource sharing causes contention that must be resolved by a resource arbiter, such as Time-Division Multiplexing. A key challenge is to configure this arbiter to satisfy the bandwidth and latency requirements of the real-time applications, while maximizing the slack capacity to improve performance of their non-real-time counterparts. As this configuration problem is NP-hard, a sophisticated automated configuration method is required to avoid negatively impacting design time. The main contributions of this article are: 1) An optimal approach that takes an existing integer linear programming (ILP) model addressing the problem and wraps it in a branch-and-price framework to improve scalability. 2) A faster heuristic algorithm that typically provides near-optimal solutions. 3) An experimental evaluation that quantitatively compares the branch-and-price approach to the previously formulated ILP model and the proposed heuristic. 4) A case study of an HD video and graphics processing system that demonstrates the practical applicability of the approach.

Tradução e legendagem do documentário: memórias do ofício

Trabalho de Projeto apresentado ao Instituto de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Tradução e Interpretação Especializadas, sob orientação do Dr. Manuel Fernando Moreira da Silva

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.

Desenvolvimento de Ontologia para Apoio ao Diagnóstico de Distúrbios do Humor

Mestrado em Computação e Instrumentação Médica

Identity and belonging in the novels of Dorn Rabinovici

This essay analyses how the different types of memory may influence the process of identity formation. It shall be argued that not only memories formed upon the subject’s experiences play a key role in this process; intermediated, received narratives from the past, memories transmitted either symbolically or by elder members of the group, or, what has been meanwhile termed as “postmemory”, also play an important part in the development of an individual’s identitary map. This theoretical framework will be illustrated with the novelistic work of Austrian Israeli-born historian, writer and political activist Doron Rabinovici (*1961). As a representative of the so-called “second generation” of Holocaust writers, a generation of individuals who did not experience the nazi genocide violence, but who had to form their identities under the shadow of such a brutal past, Rabinovici addresses essential topics such as the intergenerational transmission of memory and guilt within survivor families, identity formation of second generation individuals (Jews and non-Jews) and the question of simultaneously belonging to different social, historical and linguistic contexts.

A Generic and Compositional Framework for Multicore Response Time Analysis

23rd International Conference on Real-Time Networks and Systems (RTNS 2015). 4 to 6, Nov, 2015, Main Track. Lille, France. Best Paper Award Nominee