Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.

Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Empreitada de construção dos armazéns do polo 2 da plataforma logística do porto de Leixões - Direção e controlo da produção

A Plataforma Logística do Porto de Leixões, administrada pela Administração dos Portos do Douro e Leixões, S.A. (APDL), integra dois Polos situados no concelho de Matosinhos em locais estratégicos para o desenvolvimento das atividades portuária e de logística. É neste contexto que a empresa Luís Simões contactou a APDL no sentido de alugar um espaço para se instalar no Polo 2 da Plataforma Logística do Porto de Leixões. Para que este contrato fosse celebrado existiu um compromisso da APDL de construir dois armazéns com cerca de 10.000m2 cada e ainda um edifício administrativo com cerca de 2.900m2 e todas as redes de infraestruturas, circulações e arranjos exteriores. Após a realização de Concurso Público, a Empreitada de Construção, foi adjudicada à empresa DST - Domingos da Silva Teixeira, S.A.. O presente relatório é referente a um estágio realizado na DST, S.A., em obra, no período de 31 de Janeiro de 2014 e 31 de Julho de 2014. O estágio englobou a direção e controlo da produção das atividades de construção civil que decorreram na empreitada durante este período. O estágio foi efetuado em ambiente real de obra tendo seguido o planeamento habitual de uma empreitada. Foram desenvolvidas numa primeira fase as atividades de preparação e lançamento de consultas de subempreitadas. De seguida foram desenvolvidas tarefas de preparação, controlo de fornecimento, apoio e acompanhamento dos subempreiteiros em obra, destacando-se o acompanhamento dos trabalhos de revestimento exteriores dos edifícios e dos pavimentos de alta planimetria.