Delamination analysis of carbon fibre reinforced laminates: evaluation of a special step drill

Drilling of carbon fibre/epoxy laminates is usually carried out using standard drills. However, it is necessary to adapt the processes and/or tooling as the risk of delamination, or other damages, is high. These problems can affect mechanical properties of produced parts, therefore, lower reliability. In this paper, four different drills – three commercial and a special step (prototype) – are compared in terms of thrust force during drilling and delamination. In order to evaluate damage, enhanced radiography is applied. The resulting images were then computational processed using a previously developed image processing and analysis platform. Results show that the prototype drill had encouraging results in terms of maximum thrust force and delamination reduction. Furthermore, it is possible to state that a correct choice of drill geometry, particularly the use of a pilot hole, a conservative cutting speed – 53 m/min – and a low feed rate – 0.025 mm/rev – can help to prevent delamination.

A framework for memory contention analysis in multi-core platforms

The last decade has witnessed a major shift towards the deployment of embedded applications on multi-core platforms. However, real-time applications have not been able to fully benefit from this transition, as the computational gains offered by multi-cores are often offset by performance degradation due to shared resources, such as main memory. To efficiently use multi-core platforms for real-time systems, it is hence essential to tightly bound the interference when accessing shared resources. Although there has been much recent work in this area, a remaining key problem is to address the diversity of memory arbiters in the analysis to make it applicable to a wide range of systems. This work handles diverse arbiters by proposing a general framework to compute the maximum interference caused by the shared memory bus and its impact on the execution time of the tasks running on the cores, considering different bus arbiters. Our novel approach clearly demarcates the arbiter-dependent and independent stages in the analysis of these upper bounds. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to the contention for the bus. We show that the framework addresses the diversity problem by applying it to a memory bus shared by a fixed-priority arbiter, a time-division multiplexing (TDM) arbiter, and an unspecified work-conserving arbiter using applications from the MediaBench test suite. We also experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

Methodologies for the WCET Analysis of Parallel Applications on Many-core Architectures

Euromicro Conference on Digital System Design (DSD 2015), Funchal, Portugal.

Towards realistic core-failure-resilient scheduling and analysis

Presented at IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 4, Dec, 2015. San Antonio, U.S.A..

Towards realistic core-failure-resilient scheduling and analysis

Presented at IEEE Real-Time Systems Symposium (RTSS 2015). 1 to 4, Dec, 2015. San Antonio, U.S.A..