Task assignment algorithms for two-type heterogeneous multiprocessors

Consider the problem of assigning implicit-deadline sporadic tasks on a heterogeneous multiprocessor platform comprising two different types of processors—such a platform is referred to as two-type platform. We present two low degree polynomial time-complexity algorithms, SA and SA-P, each providing the following guarantee. For a given two-type platform and a task set, if there exists a task assignment such that tasks can be scheduled to meet deadlines by allowing them to migrate only between processors of the same type (intra-migrative), then (i) using SA, it is guaranteed to find such an assignment where the same restriction on task migration applies but given a platform in which processors are 1+α/2 times faster and (ii) SA-P succeeds in finding a task assignment where tasks are not allowed to migrate between processors (non-migrative) but given a platform in which processors are 1+α times faster. The parameter 0<α≤1 is a property of the task set; it is the maximum of all the task utilizations that are no greater than 1. We evaluate average-case performance of both the algorithms by generating task sets randomly and measuring how much faster processors the algorithms need (which is upper bounded by 1+α/2 for SA and 1+α for SA-P) in order to output a feasible task assignment (intra-migrative for SA and non-migrative for SA-P). In our evaluations, for the vast majority of task sets, these algorithms require significantly smaller processor speedup than indicated by their theoretical bounds. Finally, we consider a special case where no task utilization in the given task set can exceed one and for this case, we (re-)prove the performance guarantees of SA and SA-P. We show, for both of the algorithms, that changing the adversary from intra-migrative to a more powerful one, namely fully-migrative, in which tasks can migrate between processors of any type, does not deteriorate the performance guarantees. For this special case, we compare the average-case performance of SA-P and a state-of-the-art algorithm by generating task sets randomly. In our evaluations, SA-P outperforms the state-of-the-art by requiring much smaller processor speedup and by running orders of magnitude faster.

NoC contention analysis using a branch-and-prune algorithm

“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called “Branch and Prune” (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we introduce a more general approach, namely “Branch, Prune and Collapse” (BPC) which offers a configurable parameter that provides a flexible trade-off between the computational complexity and the tightness of the computed estimate. The recursive-calculus methods and BP present two special cases of BPC when a trade-off parameter is 1 or ∞, respectively. Through simulations, we analyze this trade-off, reason about the implications of certain choices, and also provide some case studies to observe the impact of task parameters on the WCTT estimates.

Label-free human chorionic gonadotropin detection at picogram levels using oriented antibodies bound to graphene screen-printed electrodes

Human chorionic gonadotropin (hCG) is a key diagnostic marker of pregnancy and an important biomarker for cancers in the prostate, ovaries and bladder and therefore of great importance in diagnosis. For this purpose, a new immunosensor of screen-printed electrodes (SPEs) is presented here. The device was fabricated by introducing a polyaniline (PANI) conductive layer, via in situ electropolymerization of aniline, onto a screen-printed graphene support. The PANI-coated graphene acts as the working electrode of a three terminal electrochemical sensor. The working electrode is functionalised with anti-hCG, by means of a simple process that enabled oriented antibody binding to the PANI layer. The antibody was attached to PANI following activation of the –COOH group at the Fc terminal. Functionalisation of the electrode was analysed and optimized using Electrochemical Impedance Spectroscopy (EIS). Chemical modification of the surface was characterised using Fourier transform infrared, and Raman spectroscopy with confocal microscopy. The graphene–SPE–PANI devices displayed linear responses to hCG in EIS assays from 0.001 to 50 ng mL−1 in real urine, with a detection limit of 0.286 pg mL−1. High selectivity was observed with respect to the presence of the constituent components of urine (urea, creatinine, magnesium chloride, calcium chloride, sodium dihydrogen phosphate, ammonium chloride, potassium sulphate and sodium chloride) at their normal levels, with a negligible sensor response to these chemicals. Successful detection of hCG was also achieved in spiked samples of real urine from a pregnant woman. The immunosensor developed is a promising tool for point-of-care detection of hCG, due to its excellent detection capability, simplicity of fabrication, low-cost, high sensitivity and selectivity.

Timing Analysis of Fixed Priority SelfSuspending Sporadic Tasks

27th Euromicro Conference on Real-Time Systems (ECRTS 2015), Lund, Sweden.

Considerations on the Least Upper Bound for Mixed-Criticality Real-Time Systems

5th Brazilian Symposium on Computing Systems Engineering, SBESC 2015 (SBESC 2015). 3 to 6, Nov, 2015. Foz do Iguaçu, Brasil.