Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

Reliability and availability in reconfigurable computing: a basis for a common solution

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

Sistema didáctico de baixo custo com FPGA de alta densidade

O uso das Field-Programmable Gate Array tem crescido de forma exponencial. Com isto dito, é importante que os engenheiros electrotécnicos estejam familiarizados com este tipo de tecnologia. Foi com o intuído de passar estas valências para os alunos do ISEP, que surgiu a ideia de criar um sistema didáctico, que permitisse ao alunos aprender a trabalhar com estes dispositivos. O seguinte trabalho iniciou-se com base num estudo das características destes dispositivos e das suas potencialidades, seguido de uma avaliação do que o mercado tem para oferecer. Posteriormente, com base em toda a informação reunida, foi definida a arquitectura do sistema, que levou selecção de dispositivos a incluir no mesmo, e culminando na concepção do esquema eléctrico do sistema e da placa de circuito impresso correspondente ao protótipo do mesmo. As principais directivas para este projecto foram o uso de uma FPGA de alta densidade e a concepção da ferramenta com o custo de projecto o mais reduzido possível.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

Projeto e implementação de um pré-regulador de fator de potência com controlo digital

Hoje em dia as fontes de alimentação possuem correção do fator de potência, devido às diversas normas regulamentares existentes, que introduziram grandes restrições no que respeita à distorção harmónica (THD) e fator de potência (FP). Este trabalho trata da análise, desenvolvimento e implementação de um Pré-Regulador de fator de potência com controlo digital. O controlo digital de conversores com recurso a processamento digital de sinal tem vindo a ser ao longo dos últimos anos, objeto de investigação e desenvolvimento, estando constantemente a surgirem modificações nas topologias existentes. Esta dissertação tem como objetivo estudar e implementar um Pré-Regulador Retificador Boost e o respetivo controlo digital. O controlo do conversor é feito através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL – Very High Speed Integrated Circuit Hardware Description Language) e implementado num dispositivo FPGA (Field Programmable Gate Array) Spartan-3E. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos controladores. Para efetuar este controlo é necessário adquirir os sinais da corrente de entrada, tensão de entrada e tensão de saída. O sinal resultante do módulo de controlo é um sinal de PWM com valor de fator de ciclo variável ao longo do tempo. O projeto é simulado e validado através da plataforma MatLab/Simulink e PSIM, onde são apresentados resultados para o regime permanente e para transitórios da carga e da tensão de alimentação. Finalmente, o Pré-Regulador Retificador Boost controlado de forma digital é implementado em laboratório. Os resultados experimentais são apresentados para validar a metodologia e o projeto desenvolvidos.

Construção de um variador de frequência

A dificuldade de controlo de um motor de indução, bem como o armazenamento de energia CC e posterior utilização como energia alternada promoveram o desenvolvimento de variadores de frequência e inversores. Assim, como projeto de tese de mestrado em Automação e Sistemas surge o desenvolvimento de um variador de frequência. Para elaboração do variador de frequência efetuou-se um estudo sobre as técnicas de modulação utilizadas nos inversores. A técnica escolhida e utilizada é a Sinusoidal Pulse Width Modulation (SPWM). Esta técnica baseia-se na modelação por largura de impulso (PWM), o qual é formado por comparação de um sinal de referência com um sinal de portadora de elevada frequência. Por sua vez, a topologia escolhida para o inversor corresponde a um Voltage Source Inverter (VSI) de ponte trifásica completa a três terminais. O desenvolvimento da técnica de modulação SPWM levou ao desenvolvimento de um modelo de simulação em SIMULINK, o qual permitiu retirar conclusões sobre os resultados obtidos. Na fase de implementação, foram desenvolvidas placas para o funcionamento do variador de frequência. Assim, numa fase inicial foi desenvolvida a placa de controlo, a qual contém a unidade de processamento e que é responsável pela atuação de Insulated Gate Bipolar Transistors (IGBTs). Para além disso, foi desenvolvida uma placa para proteção dos IGBTs (evitando condução simultânea no mesmo terminal) e uma placa de fontes isoladas para alimentação dos circuitos e para atuação dos IGBTs. Ainda, foi desenvolvida a técnica de SPWM em software para a unidade de controlo e finalmente foi desenvolvida uma interface gráfica para interação com o utilizador. A validação do projeto foi conseguida através da variação da velocidade do motor de indução trifásico. Para isso, este foi colocado a funcionar a diversas frequências de funcionamento e a diferentes amplitudes. Para além disso, o seu funcionamento foi também validado utilizando uma carga trifásica equilibrada de 3 lâmpadas de forma a ser visualizada a variação de frequência e variação de amplitude.

Run-time defragmentation for dynamically reconfigurable hardware

Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.

Migracion, prácticas artísticas y artivismos

Una de las potencialidades del arte es devenir una herramienta para enfocar determinados conflictos desde nuevos ángulos y articular preguntas que impacten en la comunidad. Aquí el arte se funde con la filosofía, la sociología, la antropología, con el activismo, y con la propia vida. A partir de tales parámetros, se esbozarán diversas propuestas artísticas que ilustran cómo distintos creadores abordan –desde distintos ángulos– el fenómeno de la migración Dentro de la amplia miríada de perspectivas desde las que se puede tratar la migración es interesante resaltar el trabajo de varios artistas que se transforman en altavoces de las experiencias de otras personas, tal y como ejemplifican los proyectos de Pep Dardanyà, Marisa González, He Chengyue y Josep María Martín. Desde un ángulo radicalmente distinto, Santiago Sierra y el colectivo Yes lab reproducen y llevan al límite las mismas dinámicas de explotación que critican, y para finalizar, bajo el prisma de la experiencia vivida, la artista Fiona Tan explora su propio proceso migratorio e investiga la construcción de la identidad.

The development of the N1 and N2 components in auditory oddball paradigms: a systematic review with narrative analysis and suggested normative values

Auditory event-related potentials (AERPs) are widely used in diverse fields of today’s neuroscience, concerning auditory processing, speech perception, language acquisition, neurodevelopment, attention and cognition in normal aging, gender, developmental, neurologic and psychiatric disorders. However, its transposition to clinical practice has remained minimal. Mainly due to scarce literature on normative data across age, wide spectrumof results, variety of auditory stimuli used and to different neuropsychological meanings of AERPs components between authors. One of the most prominent AERP components studied in last decades was N1, which reflects auditory detection and discrimination. Subsequently, N2 indicates attention allocation and phonological analysis. The simultaneous analysis of N1 and N2 elicited by feasible novelty experimental paradigms, such as auditory oddball, seems an objective method to assess central auditory processing. The aim of this systematic review was to bring forward normative values for auditory oddball N1 and N2 components across age. EBSCO, PubMed, Web of Knowledge and Google Scholarwere systematically searched for studies that elicited N1 and/or N2 by auditory oddball paradigm. A total of 2,764 papers were initially identified in the database, of which 19 resulted from hand search and additional references, between 1988 and 2013, last 25 years. A final total of 68 studiesmet the eligibility criteria with a total of 2,406 participants from control groups for N1 (age range 6.6–85 years; mean 34.42) and 1,507 for N2 (age range 9–85 years; mean 36.13). Polynomial regression analysis revealed thatN1latency decreases with aging at Fz and Cz,N1 amplitude at Cz decreases from childhood to adolescence and stabilizes after 30–40 years and at Fz the decrement finishes by 60 years and highly increases after this age. Regarding N2, latency did not covary with age but amplitude showed a significant decrement for both Cz and Fz. Results suggested reliable normative values for Cz and Fz electrode locations; however, changes in brain development and components topography over age should be considered in clinical practice.

Projecto e implementação de osciloscópio digital baseado na norma IEEE1451.0

Os osciloscópios digitais são utilizados em diversas áreas do conhecimento, assumindo-se no âmbito da engenharia electrónica, como instrumentos indispensáveis. Graças ao advento das Field Programmable Gate Arrays (FPGAs), os instrumentos de medição reconfiguráveis, dadas as suas vantagens, i.e., altos desempenhos, baixos custos e elevada flexibilidade, são cada vez mais uma alternativa aos instrumentos tradicionalmente usados nos laboratórios. Tendo como objectivo a normalização no acesso e no controlo deste tipo de instrumentos, esta tese descreve o projecto e implementação de um osciloscópio digital reconfigurável baseado na norma IEEE 1451.0. Definido de acordo com uma arquitectura baseada nesta norma, as características do osciloscópio são descritas numa estrutura de dados denominada Transducer Electronic Data Sheet (TEDS), e o seu controlo é efectuado utilizando um conjunto de comandos normalizados. O osciloscópio implementa um conjunto de características e funcionalidades básicas, todas verificadas experimentalmente. Destas, destaca-se uma largura de banda de 575kHz, um intervalo de medição de 0.4V a 2.9V, a possibilidade de se definir um conjunto de escalas horizontais, o nível e declive de sincronismo e o modo de acoplamento com o circuito sob análise. Arquitecturalmente, o osciloscópio é constituído por um módulo especificado com a linguagem de descrição de hardware (HDL, Hardware Description Language) Verilog e por uma interface desenvolvida na linguagem de programação Java®. O módulo é embutido numa FPGA, definindo todo o processamento do osciloscópio. A interface permite o seu controlo e a representação do sinal medido. Durante o projecto foi utilizado um conversor Analógico/Digital (A/D) com uma frequência máxima de amostragem de 1.5MHz e 14 bits de resolução que, devido às suas limitações, obrigaram à implementação de um sistema de interpolação multi-estágio com filtros digitais.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems’ CPUs. The security operations are performed by the hosts’ central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 μs to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

Recycling old screen-printed electrodes with newly designed plastic antibodies on the wall of carbon nanotubes as sensory element for in situ detection of bacterial toxins in water

Using low cost portable devices that enable a single analytical step for screening environmental contaminants is today a demanding issue. This concept is here tried out by recycling screen-printed electrodes that were to be disposed of and by choosing as sensory element a low cost material offering specific response for an environmental contaminant. Microcystins (MCs) were used as target analyte, for being dangerous toxins produced by cyanobacteria released into water bodies. The sensory element was a plastic antibody designed by surface imprinting with carefully selected monomers to ensure a specific response. These were designed on the wall of carbon nanotubes, taking advantage of their exceptional electrical properties. The stereochemical ability of the sensory material to detect MCs was checked by preparing blank materials where the imprinting stage was made without the template molecule. The novel sensory material for MCs was introduced in a polymeric matrix and evaluated against potentiometric measurements. Nernstian response was observed from 7.24 × 10−10 to 1.28 × 10−9 M in buffer solution (10 mM HEPES, 150 mM NaCl, pH 6.6), with average slopes of −62 mVdecade−1 and detection capabilities below 1 nM. The blank materials were unable to provide a linear response against log(concentration), showing only a slight potential change towards more positive potentials with increasing concentrations (while that ofthe plastic antibodies moved to more negative values), with a maximum rate of +33 mVdecade−1. The sensors presented good selectivity towards sulphate, iron and ammonium ions, and also chloroform and tetrachloroethylene (TCE) and fast response (<20 s). This concept was successfully tested on the analysis of spiked environmental water samples. The sensors were further applied onto recycled chips, comprehending one site for the reference electrode and two sites for different selective membranes, in a biparametric approach for “in situ” analysis.

Solid contact PVC membrane electrodes based on neutral or charged carriers for the selective reading of anionic sulfamethoxazole and their application to the analysis of aquaculture water

Sulfamethoxazole (SMX) is among the antibiotics employed in aquaculture for prophylactic and therapeutic reasons. Environmental and food spread may be prevented by controlling its levels in several stages of fish farming. The present work proposes for this purpose new SMX selective electrodes for the potentiometric determination of this sulphonamide in water. The selective membranes were made of polyvinyl chloride (PVC) with tetraphenylporphyrin manganese (III) chloride or cyclodextrin-based acting as ionophores. 2-nitrophenyl octyl ether was employed as plasticizer and tetraoctylammonium, dimethyldioctadecylammonium bromide or potassium tetrakis (4-chlorophenyl) borate was used as anionic or cationic additive. The best analytical performance was reported for ISEs of tetraphenylporphyrin manganese (III) chloride with 50% mol of potassium tetrakis (4-chlorophenyl) borate compared to ionophore. Nersntian behaviour was observed from 4.0 × 10−5 to 1.0 × 10−2 mol/L (10.0 to 2500 µg/mL), and the limit of detection was 1.2 × 10−5 mol/L (3.0 µg/mL). In general, the electrodes displayed steady potentials in the pH range of 6 to 9. Emf equilibrium was reached before 15 s in all concentration levels. The electrodes revealed good discriminating ability in environmental samples. The analytical application to contaminated waters showed recoveries from 96 to 106%.

XDense: A Dense Grid Sensor Network for Distributed Feature Extraction

XXXIII Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos (SBRC 2015). 15 to 19, May, 2015, III Workshop de Comunicação em Sistemas Embarcados Críticos. Vitória, Brasil.

Towards the Development of XDense, A Sensor Network for Dense Sensing

Poster in 12th European Conference on Wireless Sensor Networks (EWSN 2015). 9 to 11, Feb, 2015, pp 24-25. Porto, Portugal.