Sistema de teste de transístores bipolares de junção e de efeito de campo

O estudo das curvas características de um transístor permite conhecer um conjunto de parâmetros essenciais à sua utilização tanto no domínio da amplificação de sinais como em circuitos de comutação. Deste estudo é possível obter dados em condições que muitas vezes não constam na documentação fornecida pelos fabricantes. O trabalho que aqui se apresenta consiste no desenvolvimento de um sistema que permite de forma simples, eficiente e económica obter as curvas características de um transístor (bipolar de junção, efeito de campo de junção e efeito de campo de metal-óxido semicondutor), podendo ainda ser utilizado como instrumento pedagógico na introdução ao estudo dos dispositivos semicondutores ou no projecto de amplificadores transistorizados. O sistema é constituído por uma unidade de condicionamento de sinal, uma unidade de processamento de dados (hardware) e por um programa informático que permite o processamento gráfico dos dados obtidos, isto é, traçar as curvas características do transístor. O seu princípio de funcionamento consiste na utilização de um conversor Digital-Analógico (DAC) como fonte de tensão variável, alimentando a base (TBJ) ou a porta (JFET e MOSFET) do dispositivo a testar. Um segundo conversor fornece a variação da tensão VCE ou VDS necessária à obtenção de cada uma das curvas. O controlo do processo é garantido por uma unidade de processamento local, baseada num microcontrolador da família 8051, responsável pela leitura dos valores em corrente e em tensão recorrendo a conversores Analógico-Digital (ADC). Depois de processados, os dados são transmitidos através de uma ligação USB para um computador no qual um programa procede à representação gráfica, das curvas características de saída e à determinação de outros parâmetros característicos do dispositivo semicondutor em teste. A utilização de componentes convencionais e a simplicidade construtiva do projecto tornam este sistema económico, de fácil utilização e flexível, pois permite com pequenas alterações

Controlador Boundary-Scan

A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

Bancada didáctica para simulação de uma Unidade de Microgeração

Neste trabalho é desenvolvida uma bancada didáctica que permite simular o funcionamento de um sistema de microgeração. A bancada inclui uma máquina síncrona responsável pela geração de energia eléctrica acoplada a uma máquina de indução que simula a máquina primária. A máquina de indução é controlada por um sistema electrónico de controlo de potência (variador de velocidade) que permite manter constante a velocidade de rotação e consequentemente a frequência da tensão gerada pela máquina síncrona. Por sua vez, a excitação da máquina síncrona é controla por uma fonte de tensão externa. A parametrização e controlo do variador de velocidade, assim como o controlo da fonte de tensão externa, são feitos a partir dum software que corre num PC, que também monitoriza a tensão gerada pela máquina síncrona. Este software é ainda responsável pela interface com o utilizador. O software desenvolvido permite manter as características da tensão gerada pela máquina síncrona independentemente da carga imposta.

Reliable real-time communication in CAN networks

Controller area network (CAN) is a fieldbus network suitable for small-scale distributed computer controlled systems (DCCS), being appropriate for sending and receiving short real-time messages at speeds up to 1 Mbit/sec. Several studies are available on how to guarantee the real-time requirements of CAN messages, providing preruntime schedulability conditions to guarantee the real-time communication requirements of DCCS traffic. Usually, it is considered that CAN guarantees atomic multicast properties by means of its extensive error detection/signaling mechanisms. However, there are some error situations where messages can be delivered in duplicate or delivered only by a subset of the receivers, leading to inconsistencies in the supported applications. In order to prevent such inconsistencies, a middleware for reliable communication in CAN is proposed, taking advantage of CAN synchronous properties to minimize the runtime overhead. Such middleware comprises a set of atomic multicast and consolidation protocols, upon which the reliable communication properties are guaranteed. The related timing analysis demonstrates that, in spite of the extra stack of protocols, the real-time properties of CAN are preserved since the predictability of message transfer is guaranteed.

Programming atomic multicasts in CAN

In Distributed Computer-Controlled Systems (DCCS), a special emphasis must be given to the communication infrastructure, which must provide timely and reliable communication services. CAN networks are usually suitable to support small-scale DCCS. However, they are known to present some reliability problems, which can lead to an unreliable behaviour of the supported applications. In this paper, an atomic multicast protocol for CAN networks is proposed. This protocol explores the CAN synchronous properties, providing a timely and reliable service to the supported applications. The implementation of such protocol in Ada, on top of the Ada version of Real-Time Linux is presented, which is used to demonstrate the advantages and disadvantages of the platform to support reliable communications in DCCS.

Symbolic fractional dynamics

Fractional dynamics reveals long range memory properties of systems described by means of signals represented by real numbers. Alternatively, dynamical systems and signals can adopt a representation where states are quantified using a set of symbols. Such signals occur both in nature and in man made processes and have the potential of a aftermath as relevant as the classical counterpart. This paper explores the association of Fractional calculus and symbolic dynamics. The results are visualized by means of the multidimensional technique and reveal the association between the fractal dimension and one definition of fractional derivative.

Fractional order modelling of fractional-order holds

Discrete time control systems require sample- and-hold circuits to perform the conversion from digital to analog. Fractional-Order Holds (FROHs) are an interpolation between the classical zero and first order holds and can be tuned to produce better system performance. However, the model of the FROH is somewhat hermetic and the design of the system becomes unnecessarily complicated. This paper addresses the modelling of the FROHs using the concepts of Fractional Calculus (FC). For this purpose, two simple fractional-order approximations are proposed whose parameters are estimated by a genetic algorithm. The results are simple to interpret, demonstrating that FC is a useful tool for the analysis of these devices.

Enhanced Race-to-halt: a leakage-aware energy management approach for dynamic priority systems

With progressing CMOS technology miniaturization, the leakage power consumption starts to dominate the dynamic power consumption. The recent technology trends have equipped the modern embedded processors with the several sleep states and reduced their overhead (energy/time) of the sleep transition. The dynamic voltage frequency scaling (DVFS) potential to save energy is diminishing due to efficient (low overhead) sleep states and increased static (leakage) power consumption. The state-of-the-art research on static power reduction at system level is based on assumptions that cannot easily be integrated into practical systems. We propose a novel enhanced race-to-halt approach (ERTH) to reduce the overall system energy consumption. The exhaustive simulations demonstrate the effectiveness of our approach showing an improvement of up to 8 % over an existing work.

Modeling of the lung impedance using a fractional order ladder network with constant phase elements

The self similar branching arrangement of the airways makes the respiratory system an ideal candidate for the application of fractional calculus theory. The fractal geometry is typically characterized by a recurrent structure. This study investigates the identification of a model for the respiratory tree by means of its electrical equivalent based on intrinsic morphology. Measurements were obtained from seven volunteers, in terms of their respiratory impedance by means of its complex representation for frequencies below 5 Hz. A parametric modeling is then applied to the complex valued data points. Since at low-frequency range the inertance is negligible, each airway branch is modeled by using gamma cell resistance and capacitance, the latter having a fractional-order constant phase element (CPE), which is identified from measurements. In addition, the complex impedance is also approximated by means of a model consisting of a lumped series resistance and a lumped fractional-order capacitance. The results reveal that both models characterize the data well, whereas the averaged CPE values are supraunitary and subunitary for the ladder network and the lumped model, respectively.

Fitness function evaluation through fractional algorithms

This paper proposes a Genetic Algorithm (GA) for the design of combinational logic circuits. The fitness function evaluation is calculated using Fractional Calculus. This approach extends the classical fitness function by including a fractional-order dynamical evaluation. The experiments reveal superior results when comparing with the classical method.

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.

Adapting remote labs to learning scenarios: case studies using VISIR and RemotElectLab

Remote laboratories are an emergent technological and pedagogical tool at all education levels, and their widespread use is an important part of their own improvement and evolution. This paper describes several issues encountered on laboratorial classes, on higher education courses, when using remote laboratories based on PXI systems, either using the VISIR system or an alternate in-house solution. Three main issues are presented and explained, all reported by teachers, that gave support to students' use of remote laboratories. The first issue deals with the need to allow students to select the actual place where an ammeter is to be inserted on electric circuits, even incorrectly, therefore emulating real-world difficulties. The second one deals with problems with timing when several measurements are required at short intervals, as in the discharge cycle of a capacitor. In addition, the last issue deals with the use of a multimeter in dc mode when reading ac values, a use that collides with the lab settings. All scenarios are presented and discussed, including the solution found for each case. The conclusion derived from the described work is that the remote laboratories area is an expanding field, where practical use leads to improvement and evolution of the available solutions, requiring a strict cooperation and information-sharing between all actors, i.e., developers, teachers, and students.

A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.

Board-level prototype validation: a built-in controller and extended BST architecture

Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.