Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Task-oriented training and lower limb strengthening to improve balance and function after stroke: a pilot study

This study investigated the effects of task-oriented training and strengthening of the affected lower limb on balance and function in people who have suffered a stroke. Sixteen male adults, with a mean age of 58 (SD 6.3) years, undergoing outpatient physiotherapy less than 1 month after a single stroke in the territory of the middle cerebral artery were recruited. Participants were allocated to one of two groups: the strengthening group (SG) or control group (CG). The main measures used were the Berg Balance Scale (BBS), Barthel Index (BI) and Modified Ashworth Scale (MAS). After 12 weeks of intervention, both groups showed improvements in outcome measures. For BBS, there was a significant difference between groups, with an increase of 26 points in the SG and 11 points in the CG. For BI, the SG improved by 39 points and the CG improved by 22 points. After intervention, the difference between groups was not significant. For MAS, differences were not significant, showing that for both groups intervention programmes did not increase spasticity. In conclusion, physiotherapy intervention for postural control dysfunctions after stroke seems to benefit from strength training of the affected lower limb and the practising functional tasks. A large randomized controlled trial is recommended to further investigate the effects of this intervention.