Simulation model for driving dynamics, energy use and power supply

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Energia

Control of a power supply with cycling current using different controllers

Fast Field Cycling (FFC) Nuclear Magnetic Resonance (NMR) relaxometers require controlled current sources in order to get accurate flux density with respect to its magnet. The main elements of the proposed solution are a power semiconductor, a DC voltage source and the magnet. The power semiconductor is commanded in order to get a linear control of the flux density. To implement the flux density control, a Hall Effect sensor is used. Furthermore, the dynamic behavior of the current source is analyzed and compared when using a PI controller and a PD2I controller.

Control of a power supply with cycling current using different controllers

Fast Field Cycling (FFC) Nuclear Magnetic Resonance (NMR) relaxometers require controlled current sources in order to get accurate flux density with respect to its magnet. The main elements of the proposed solution are a power semiconductor, a DC voltage source and the magnet. The power semiconductor is commanded in order to get a linear control of the flux density. To implement the flux density control, a Hall Effect sensor is used. Furthermore, the dynamic behavior of the current source is analyzed and compared when using a PI controller and a PD2I controller.

Reversible current power supply for fast-field cycling nuclear magnetic resonance equipment

The Fast Field-Cycling Nuclear Magnetic Resonance (FFC-NMR) is a technique used to study the molecular dynamics of different types of materials. The main elements of this equipment are a magnet and its power supply. The magnet used as reference in this work is basically a ferromagnetic core with two sets of coils and an air-gap where the materials' sample is placed. The power supply should supply the magnet being the magnet current controlled in order to perform cycles. One of the technical issues of this type of solution is the compensation of the non-linearities associated to the magnetic characteristic of the magnet and to parasitic magnetic fields. To overcome this problem, this paper describes and discusses a solution for the FFC-NMR power supply based on a four quadrant DC/DC converter.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

RF Receiver Front End for 28.5 GHz Applications on a 70 GHz F-T SiGe BiCMOS Process

This article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system-level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14 5 dB. The receiver operates from a 2 5 V power supply with a total current consumption of 31 mA.

A Step-up mu-Power Converter for Solar Energy Harvesting Applications, using Hill Climbing Maximum Power Point Tracking

This paper presents a step-up micro-power converter for solar energy harvesting applications. The circuit uses a SC voltage tripler architecture, controlled by an MPPT circuit based on the Hill Climbing algorithm. This circuit was designed in a 0.13 mu m CMOS technology in order to work with an a-Si PV cell. The circuit has a local power supply voltage, created using a scaled down SC voltage tripler, controlled by the same MPPT circuit, to make the circuit robust to load and illumination variations. The SC circuits use a combination of PMOS and NMOS transistors to reduce the occupied area. A charge re-use scheme is used to compensate the large parasitic capacitors associated to the MOS transistors. The simulation results show that the circuit can deliver a power of 1266 mu W to the load using 1712 mu W of power from the PV cell, corresponding to an efficiency as high as 73.91%. The simulations also show that the circuit is capable of starting up with only 19% of the maximum illumination level.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

A DC Voltage-Multiplier Circuit Working as a High-Voltage Pulse Generator

The intensive use of semiconductor devices enabled the development of a repetitive high-voltage pulse-generator topology from the dc voltage-multiplier (VM) concept. The proposed circuit is based on an odd VM-type circuit, where a number of dc capacitors share a common connection with different voltage ratings in each one, and the output voltage comes from a single capacitor. Standard VM rectifier and coupling diodes are used for charging the energy-storing capacitors, from an ac power supply, and two additional on/off semiconductors in each stage, to switch from the typical charging VM mode to a pulse mode with the dc energy-storing capacitors connected in series with the load. Results from a 2-kV experimental prototype with three stages, delivering a 10-mu s pulse with a 5-kHz repetition rate into a resistive load, are discussed. Additionally, the proposed circuit is compared against the solid-state Marx generator topology for the same peak input and output voltages.

Modelização de um mecanismo de levitação supercondutor para um sistema de volante de inércia comercial

Este trabalho teve como objectivo o estudo de um sistema de levitação magnética com chumaceiras supercondutoras, para utilização numa fonte de alimentação de energia eléctrica ininterrupta, que usa um volante de inércia como sistema de armazenamento de energia. Partindo de um modelo comercial existente, foi modelizada a substituição do sistema de levitação por um sistema com chumaceiras supercondutoras. Foi feito o dimensionamento do magnete permanente e do supercondutor de forma a atingir-se a força de levitação magnética necessária para elevar o rotor da máquina, garantindo simultaneamente a máxima estabilidade do sistema. Os perfis de distribuição do campo magnético no volante de inércia foram modelizados recorrendo ao método dos elementos finitos, através da utilização do software Ansys. O cálculo da força de levitação foi efectuado recorrendo ao software MATHEMATICA.

Análise dos métodos de medição dos parâmetros geométricos de via e correlação entre os dados obtidos

A razão atribuída à escolha do tema do T.F.M. em Caminhos-de-ferro, tem a ver com o facto de ser uma via de comunicação específica. Contrariamente ao que acontece na execução de auto-estradas, no caminho-de-ferro, a gestora da infra-estrutura responsabiliza-se pela execução, exploração (sinalização e controlo de circulação), abastecimento de energia fornecida às vias que dispõem de catenária (tracção eléctrica), manutenção e conservação da via. O processo de análise e inspecção de geometria de via, é usado quando e necessário preservar a infra-estrutura. Este processo iniciou-se nos caminhos-de-ferro portugueses, há muitos anos, depois da inauguração do primeiro troco de linha férrea. A primeira viagem ocorre em Outubro de 1856, sendo o início do processo em 1968, com a dresina “Matisa PV-6”. Em 1991 a C.P. adquiriu outro veículo de inspecção de via, tendo sido escolhido o VIV02 EM 120 da marca Plasser & Theurer, para substituir “Matisa PV-6”. O tema Análise dos Métodos de Medição dos Parâmetros Geométricos de Via e Correlação entre os Dados Obtidos está directamente relacionado com a manutenção e conservação de via. Na Unidade Operacional Sul (hoje ROS – Região Operacional Sul), local onde desenvolvi o T.F.M., não existem obras de construção de caminhos-de-ferro que pudesse acompanhar e constituir tema para o meu trabalho. Na realidade, com a falta de investimento que se perspectiva no futuro próximo, a manutenção da infra-estrutura passa a ser a actividade principal desenvolvida pela REFER, de modo a assegurar a comodidade, segurança e rapidez na deslocação de cargas e pessoas. A Analise Geométrica de Via e actualmente uma das principais actividades no âmbito da manutenção, que é feita por diagnóstico, contrariamente ao que acontecia no passado em que a conservação metódica era realizada num determinado ano num troço seleccionado independentemente da necessidade ou não da mesma. Uma ajuda preciosa, no que se refere à decisão de se realizar um determinado trabalho de conservação, e a do veículo VIV02 EM 120 que faz inspeções ao longo de toda a rede ferroviária e permite recolher dados e classificar através do desvio padrão, troços com extensão de 200 metros, obtendo os dados relevantes sobre a necessidade de intervenção. Para além do referido veículo existem também equipamentos ligeiros de inspecção dos parâmetros geométricos de via. Um desses equipamentos designa-se por Trólei, não sendo motorizado, pois o mesmo é movido manualmente por um operador. Obviamente que este equipamento não faz a inspecção a toda a rede pois a operação de medição é morosa, sendo contudo utilizado para análise de defeitos geométricos em pequenos trocos, tornando-se assim uma mais-valia, evitando o deslocar de um equipamento “pesado” como o VIV 02 EM 120. Para atingir os objectivos deste trabalho realizaram-se testes de medição com ambos (veiculo e equipamento ligeiro), no mesmo espaço temporal e com as mesmas características físicas, como a temperatura, humidade etc. Os resultados, de acordo com os objectivos, são a comparação entre as medições de ambos, com vista a comprovar a sua utilidade e necessidade, de acordo com os vários tipos de superstruturas constituintes da rede ferroviária nacional.

Transformador para fonte de alta-tensão contínua

Dissertação para a obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Fonte de carga de condensadores de alta tensão com compensação de fator potência

Trabalho Final de Mestrado para a obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Projecto, montagem e teste de uma unidade modular de detecção de radiação Geiger-Muller

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial