Direct Color Sensor, Optical Amplifier and Demux Device Integrated on a Single Monolithic SiC Photodetector

A pi'n/pin a-SiC:H voltage and optical bias controlled device is presented and its behavior as image and color sensor, optical amplifier and demux device is discussed. The design and the light source properties are correlated with the sensor output characteristics. Different readout techniques are used. When a low power monochromatic scanner readout the generated carriers the transducer recognizes a color pattern projected on it acting as a direct color and image sensor. Scan speeds up to 10(4) lines per second are achieved without degradation in the resolution. If the photocurrent generated by different monochromatic pulsed channels is readout directly, the information is demultiplexed. Results show that it is possible to decode the information from three simultaneous color channels without bit errors at bit rates per channel higher than 4000 bps. Finally, when triggered by light of appropriated wavelength, it can amplify or suppress the generated photocurrent working as an optical amplifier (C) 2009 Published by Elsevier Ltd.

Wavelength Selective a-SiC:H p-i-n/p-i-n Heterostructure for Fluorescent Proteins Detection

In this paper we present results on the optimization of multilayered a-SiC:H heterostructures that can be used as optical transducers for fluorescent proteins detection using the Fluorescence Resonance Energy Transfer approach. Double structures composed by pin based aSiC:H cells are analyzed. The color discrimination is achieved by ac photocurrent measurement under different externally applied bias. Experimental data on spectral response analysis, current-voltage characteristics and color and transmission rate discrimination are reported. An electrical model, supported by a numerical simulation gives insight into the device operation. Results show that the optimized a-SiC:H heterostructures act as voltage controlled optical filters in the visible spectrum. When the applied voltages are chosen appropriately those optical transducers can detect not only the selective excitation of specimen fluorophores, but also the subsequent weak acceptor fluorescent channel emission.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

A 5GHz/1.8V CMOS Active Balun Integrated with LNA

The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

Comportamento à fadiga de juntas soldadas de aços tipo 460M com fios fluxados

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Pontes integrais: estado da arte

Dissertação para obtenção do grau de mestre em Engenharia Civil