20 resultados para Circuit of Sacoleiros

em Repositório Científico do Instituto Politécnico de Lisboa - Portugal


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A new circuit topology is proposed to replace the actual pulse transformer and thyratron based resonant modulator that supplies the 60 kV target potential for the ion acceleration of the On-Line Isotope Mass Separator accelerator, the stability of which is critical for the mass resolution downstream separator, at the European Organization for Nuclear Research. The improved modulator uses two solid-state switches working together, each one based on the Marx generator concept, operating as series and parallel switches, reducing the stress on the series stacked semiconductors, and also as auxiliary pulse generator in order to fulfill the target requirements. Preliminary results of a 10 kV prototype, using 1200 V insulated gate bipolar transistors and capacitors in the solid-state Marx circuits, ten stages each, with an electrical equivalent circuit of the target, are presented, demonstrating both the improved voltage stability and pulse flexibility potential wanted for this new modulator.

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The main objective of this work was to evaluate the hypothesis that the greater transfer stability leads also to less volume of fumes. Using an Ar + 25%CO2 blend as shielding gas and maintaining constant the average current, wire feed speed and welding speed, bead-on-plate welds were carried out with plain carbon steel solid wire. The welding voltage was scanned to progressively vary the transfer stability. Using two conditions of low stability and one with high stability, fume generation was evaluated by means of the AWS F1.2:2006 standard. The influence of these conditions on fume morphology and composition was also verified. A condition with greater transfer stability does not generate less fume quantity, despite the fact that this condition produces fewer spatters. Other factors such as short-circuit current, arcing time, droplet diameters and arc length are the likely governing factors, but in an interrelated way. Metal transfer stability does not influence either the composition or the size/morphology of fume particulates. (c) 2014 Elsevier B.V. All rights reserved.

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The intensive use of semiconductor devices enabled the development of a repetitive high-voltage pulse-generator topology from the dc voltage-multiplier (VM) concept. The proposed circuit is based on an odd VM-type circuit, where a number of dc capacitors share a common connection with different voltage ratings in each one, and the output voltage comes from a single capacitor. Standard VM rectifier and coupling diodes are used for charging the energy-storing capacitors, from an ac power supply, and two additional on/off semiconductors in each stage, to switch from the typical charging VM mode to a pulse mode with the dc energy-storing capacitors connected in series with the load. Results from a 2-kV experimental prototype with three stages, delivering a 10-mu s pulse with a 5-kHz repetition rate into a resistive load, are discussed. Additionally, the proposed circuit is compared against the solid-state Marx generator topology for the same peak input and output voltages.

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As wind power generation undergoes rapid growth, lightning and overvoltage incidents involving wind power plants have come to be regarded as a serious problem. Firstly, lightning location systems are discussed, as well as important parameters regarding lightning protection. Also, this paper presents a case study, based on a wind turbine with an interconnecting transformer, for the study of adequate lightning and overvoltage protection measures. The electromagnetic transients circuit under study is described, and computational results are presented.

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This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

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ZnO:Al/p (SiC:H)/i (Si:H)/n (SiC:H) large area image and colour sensor are analysed. Carrier transport and collection efficiency are investigated from dark and illuminated current-voltage (I-V) dependence and spectral response measurements under different optical and electrical bias conditions. Results show that the carrier collection depends on the optical bias and on the applied voltage. By changing the electrical bias around the open circuit voltage it is possible to filter the absorption at a given wavelength and so to tune the spectral sensitivity of the device. Transport and optical modelling give insight into the internal physical process and explain the bias control of the spectral response and the image and colour sensing properties of the devices.

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A Blumlein line is a particular Pulse Forming Line, PFL, configuration that allows the generation of high-voltage sub-microsecond square pulses, with the same voltage amplitude as the dc charging voltage, into a matching load. By stacking n Blumlein lines one can multiply in theory by n the input dc voltage charging amplitude. In order to understand the operating behavior of this electromagnetic system and to further optimize its operation it is fundamental to theoretically model it, that is to calculate the voltage amplitudes at each circuit point and the time instant that happens. In order to do this, one needs to define the reflection and transmission coefficients where impedance discontinuity occurs. The experimental results of a fast solid-state switch, which discharges a three stage Blumlein stack, will be compared with theoretical ones.

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Characteristics of tunable wavelength filters based on a-SiC:H multi-layered stacked cells are studied both theoretically and experimentally. Results show that the light-activated photonic device combines the demultiplexing operation with the simultaneous photodetection and self amplification of an optical signal. The sensor is a bias wavelength current-controlled device that make use of changes in the wavelength of the background to control the power delivered to the load, acting a photonic active filter. Its gain depends on the background wavelength that controls the electrical field profile across the device.

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A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitorvoltage tripler architecture with MOSFET capacitors, which results in an, area approximately eight times smaller than using MiM capacitors for the 0.131mu m CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit is self-clocked, using a phase controller designed specifically to work with an amorphous silicon solar cell, in order to obtain themaximum available power from the cell. This will be done by tracking its maximum power point (MPPT) using the fractional open circuit voltage method. Electrical simulations of the circuit, together with an equivalent electrical model of an amorphous silicon solar cell, show that the circuit can deliver apower of 1132 mu W to the load, corresponding to a maximum efficiency of 66.81%.

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A voltage limiter circuit for indoor light energy harvesting applications is presented. This circuit is a part of a bigger system, whose function is to harvest indoor light energy, process it and store it, so that it can be used at a later time. This processing consists on maximum power point tracking (MPPT) and stepping-up, of the voltage from the photovoltaic (PV) harvester cell. The circuit here described, ensures that even under strong illumination, the generated voltage will not exceed the limit allowed by the technology, avoiding the degradation, or destruction, of the integrated die. A prototype of the limiter circuit was designed in a 130 nm CMOS technology. The layout of the circuit has a total area of 23414 mu m(2). Simulation results, using Spectre, are presented.

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This paper presents a new driving scheme utilizing an in-pixel metal-insulator-semiconductor (MIS) photosensor for luminance control of active-matrix organic light-emitting diode (AMOLED) pixel. The proposed 3-TFT circuit is controlled by an external driver performing the signal readout, processing, and programming operations according to a luminance adjusting algorithm. To maintain the fabrication simplicity, the embedded MIS photosensor shares the same layer stack with pixel TFTs. Performance characteristics of the MIS structure with a nc-Si : H/a-Si : H bilayer absorber were measured and analyzed to prove the concept. The observed transient dark current is associated with charge trapping at the insulator-semiconductor interface that can be largely eliminated by adjusting the bias voltage during the refresh cycle. Other factors limiting the dynamic range and external quantum efficiency are also determined and verified using a small-signal model of the device. Experimental results demonstrate the feasibility of the MIS photosensor for the discussed driving scheme.

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A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm(2). Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

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Following work on tantalum and chromium implanted flat M50 steel substrates, this work reports on the electrochemical behaviour of M50 steel implanted with tantalum and chromium and the effect of the angle of incidence. Proposed optimum doses for resistance to chloride attack were based on the interpretation of results obtained during long-term and accelerated electrochemical testing. After dose optimization from the corrosion viewpoint, substrates were implanted at different angles of incidence (15°, 30°, 45°, 60°, 75°, 90°) and their susceptibility to localized corrosion assessed using open-circuit measurements, step by step polarization and cyclic voltammetry at several scan rates (5–50 mV s-1). Results showed, for tantalum implanted samples, an ennoblement of the pitting potential of approximately 0.5 V for an angle of incidence of 90°. A retained dose of 5 × 1016 atoms cm-2 was found by depth profiling with Rutherford backscattering spectrometry. The retained dose decreases rapidly with angle of incidence. The breakdown potential varies roughly linearly with the angle of incidence up to 30° falling fast to reach -0.1 V (vs. a saturated calomel electrode (SCE)) for 15°. Chromium was found to behave differently. Maximum corrosion resistance was found for angles of 45°–60° according to current densities and breakdown potentials. Cr+ depth profiles ((p,γ) resonance broadening method), showed that retained doses up to an angle of 60° did not change much from the implanted dose at 90°, 2 × 1017 Cr atoms cm-2. The retained implantation dose for tantalum and chromium was found to follow a (cos θ)8/3 dependence where θ is the angle between the sample normal and the beam direction.

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Radio frequency (RF) energy harvesting is an emerging technology that will enable to drive the next generation of wireless sensor networks (WSNs) without the need of using batteries. In this paper, we present RF energy harvesting circuits specifically developed for GSM bands (900/1800) and a wearable dual-band antenna suitable for possible implementation within clothes for body worn applications. Besides, we address the development and experimental characterization of three different prototypes of a five-stage Dickson voltage multiplier (with match impedance circuit) responsible for harvesting the RF energy. Different printed circuit board (PCB) fabrication techniques to produce the prototypes result in different values of conversion efficiency. Therefore, we conclude that if the PCB fabrication is achieved by means of a rigorous control in the photo-positive method and chemical bath procedure applied to the PCB it allows for attaining better values for the conversion efficiency. All three prototypes (1, 2 and 3) can power supply the IRIS sensor node for RF received powers of -4 dBm, -6 dBm and -5 dBm, and conversion efficiencies of 20, 32 and 26%, respectively. © 2014 IEEE.

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Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).