An efficient scalable RNS architecture for large dynamic ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

Computing the phase diagram of binary mixtures: A patchy particle case study

We investigate the phase behaviour of 2D mixtures of bi-functional and three-functional patchy particles and 3D mixtures of bi-functional and tetra-functional patchy particles by means of Monte Carlo simulations and Wertheim theory. We start by computing the critical points of the pure systems and then we investigate how the critical parameters change upon lowering the temperature. We extend the successive umbrella sampling method to mixtures to make it possible to extract information about the phase behaviour of the system at a fixed temperature for the whole range of densities and compositions of interest. (C) 2013 AIP Publishing LLC.

ROM-less RNS-to-binary converter moduli {22N − 1, 22N + 1, 2N − 3, 2N + 3}

In this paper, a novel ROM-less RNS-to-binary converter is proposed, using a new balanced moduli set {22n-1, 22n + 1, 2n-3, 2n + 3} for n even. The proposed converter is implemented with a two stage ROM-less approach, which computes the value of X based only in arithmetic operations, without using lookup tables. Experimental results for 24 to 120 bits of Dynamic Range, show that the proposed converter structure allows a balanced system with 20% faster arithmetic channels regarding the related state of the art, while requiring similar area resources. This improvement in the channel's performance is enough to offset the higher conversion costs of the proposed converter. Furthermore, up to 20% better Power-Delay-Product efficiency metric can be achieved for the full RNS architecture using the proposed moduli set. © 2014 IEEE.

Arithmetic-based binary-to-RNS converter modulo {2(n)+/- k} for jn-Bit dynamic range

In this brief, a read-only-memoryless structure for binary-to-residue number system (RNS) conversion modulo {2(n) +/- k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing {2(n) +/- k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the {2(n) +/- k} moduli is performed.