Explorador integrado de serviços de armazenamento na cloud: cloud cockpit

Projeto para obtenção do grau de Mestre em Engenharia Informática e de Computadores

Towards an Academic Social Network for Bologna Process

The Bologna Process aimed to build a European Higher Education Area promoting student's mobility. The adoption of Bologna Declaration directives requires a self management distributed approach to deal with student's mobility, allowing frequent updates in institutions rules or legislation. This paper suggests a computational system architecture, which follows a social network design. A set of structured annotations is proposed in order to organize the user's information. For instance, when the user is a student its annotations are organized into an academic record. The academic record data is used to discover interests, namely mobility interests, among students that belongs the academic network. These ideas have been applied into a demonstrator that includes a mobility simulator to compare and show the student's academic evolution.

Operação em ambiente móvel baseado em modelo de mercado

Projecto Final para obtenção do grau de Mestre em Engenharia Informática e de Computadores

An efficient scalable RNS architecture for large dynamic ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

An ultrasound based computer-aided diagnosis tool for steatosis detection

Liver steatosis is a common disease usually associated with social and genetic factors. Early detection and quantification is important since it can evolve to cirrhosis. In this paper, a new computer-aided diagnosis (CAD) system for steatosis classification, in a local and global basis, is presented. Bayes factor is computed from objective ultrasound textural features extracted from the liver parenchyma. The goal is to develop a CAD screening tool, to help in the steatosis detection. Results showed an accuracy of 93.33%, with a sensitivity of 94.59% and specificity of 92.11%, using the Bayes classifier. The proposed CAD system is a suitable graphical display for steatosis classification.

A biosignal embedded system for physiological computing

Thesis submitted in the fulfilment of the requirements for the Degree of Master in Electronic and Telecomunications Engineering

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

Embedded System for ECG Biometrics

Comunication in Internationa Conference with Peer Review First International Congress on Cardiovasular Technologies - CARDIOTECHNIX, Vilamoura, Portugal, 2013

Avaliação da caracterização de lesões em mamografia com recurso a sistemas CAD (Computer-Aided Diagnosis)

Os sistemas Computer-Aided Diagnosis (CAD) auxiliam a deteção e diferenciação de lesões benignas e malignas, aumentando a performance no diagnóstico do cancro da mama. As lesões da mama estão fortemente correlacionadas com a forma do contorno: lesões benignas apresentam contornos regulares, enquanto as lesões malignas tendem a apresentar contornos irregulares. Desta forma, a utilização de medidas quantitativas, como a dimensão fractal (DF), pode ajudar na caracterização dos contornos regulares ou irregulares de uma lesão. O principal objetivo deste estudo é verificar se a utilização concomitante de 2 (ou mais) medidas de DF – uma tradicionalmente utilizada, a qual foi designada por “DF de contorno”; outra proposta por nós, designada por “DF de área” – e ainda 3 medidas obtidas a partir destas, por operações de dilatação/erosão e por normalização de uma das medidas anteriores, melhoram a capacidade de caracterização de acordo com a escala BIRADS (Breast Imaging Reporting and Data System) e o tipo de lesão. As medidas de DF (DF contorno e DF área) foram calculadas através da aplicação do método box-counting, diretamente em imagens de lesões segmentadas e após a aplicação de um algoritmo de dilatação/erosão. A última medida baseia-se na diferença normalizada entre as duas medidas DF de área antes e após a aplicação do algoritmo de dilatação/erosão. Os resultados demonstram que a medida DF de contorno é uma ferramenta útil na diferenciação de lesões, de acordo com a escala BIRADS e o tipo de lesão; no entanto, em algumas situações, ocorrem alguns erros. O uso combinado desta medida com as quatro medidas propostas pode melhorar a classificação das lesões.

A Compact and Scalable RNS Architecture

Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

Personalized public transportation information

Thesis to obtain the Master of Science Degree in Computer Science and Engineering

Mobile cockpit system for enhanced electric bicycle use

This paper presents the project of a mobile cockpit system (MCS) for smartphones, which provides assistance to electric bicycle (EB) cyclists in smart cities' environment. The presented system introduces a mobile application (MCS App) with the goal to provide useful personalized information to the cyclist related to the EB's use, including EB range prediction considering the intended path, management of the cycling effort performed by the cyclist, handling of the battery charging process, and the provisioning of information regarding available public transport. This work also introduces the EB cyclist profile concept, which is based on historical data analysis previously stored in a database and collected from mobile devices' sensors. From the tests performed, the results show the importance of route guidance, taking into account the energy savings. The results also show significant changes on range prediction based on user and route taken. It is important to say that the proposed system can be used for all bicycles in general.

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.