Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Uma história de interior: argumento e guião

Este trabalho de desenvolvimento surge como complemento de uma história (argumento e guião) criada e desenvolvida, de maneira a ser filmada num futuro próximo. O meu projeto final, que me confere o grau de mestre, é pois, o desenvolvimento de um argumento e guião, apoiado num trabalho de pesquisa e desenvolvimento, que no seu todo, justifique a minha história. A minha história é muito particular porque está diretamente ligada com as minhas raízes, com a minha educação e com a forma como eu vejo o mundo. Para mim, a identidade cinematográfica, surge como um produto de um contexto cultural onde é concebida. Ou seja, esta obra, surge principalmente devido às minhas origens transmontanas, à forma como vejo aquela região e como a destaco da vida citadina. A cultura daquela região é uma cultura essencialmente portuguesa. É uma cultura que identifica um país, através de um produto internacionalmente comercializado, o vinho do Porto. Procurei enquadrar este trabalho, com as tendências do cinema português contemporâneo. Procurei perceber o que foi filmado, escrito e imortalizado sobre aquela região - a minha região. Através de uma pesquisa sobre a história do cinema português e suas principais mudanças, consegui evidenciar tudo aquilo que particularmente me influenciou ao longo deste desenvolvimento.

Matrix converter as unified power flow controller: design and implementation of decoupled direct power controllers

This paper presents the design and implementation of direct power controllers for three-phase matrix converters (MC) operating as Unified Power Flow Controllers (UPFC). Theoretical principles of the decoupled linear power controllers of the MC-UPFC to minimize the cross-coupling between active and reactive power control are established. From the matrix converter based UPFC model with a modified Venturini high frequency PWM modulator, decoupled controllers for the transmission line active (P) and reactive (Q) power direct control are synthesized. Simulation results, obtained from Matlab/Simulink, are presented in order to confirm the proposed approach. Results obtained show decoupled power control, zero error tracking, and fast responses with no overshoot and no steady-state error.

High-level Petri nets modules for embedded controllers design

Modular design is crucial to manage large-scale systems and to support the divide-and-conquer development approach. It allows hierarchical representations and, therefore, one can have a system overview, as well as observe component details. Petri nets are suitable to model concurrent systems, but lack on structuring mechanisms to support abstractions and the composition of sub-models, in particular when considering applications to embedded controllers design. In this paper we present a module construct, and an underlying high-level Petri net type, to model embedded controllers. Multiple interfaces can be declared in a module, thus, different instances of the same module can be used in different situations. The interface is a subset of the module nodes, through which the communication with the environment is made. Module places can be annotated with a generic type, overridden with a concrete type at instance level, and constants declared in a module may have a new value in each instance.

Multiobjective design of viscoelastic laminated composite sandwich panels

The optimal design of laminated sandwich panels with viscoelastic core is addressed in this paper, with the objective of simultaneously minimizing weight and material cost and maximizing modal damping. The design variables are the number of layers in the laminated sandwich panel, the layer constituent materials and orientation angles and the viscoelastic layer thickness. The problem is solved using the Direct MultiSearch (DMS) solver for multiobjective optimization problems which does not use any derivatives of the objective functions. A finite element model for sandwich plates with transversely compressible viscoelastic core and anisotropic laminated face layers is used. Trade-off Pareto optimal fronts are obtained and the results are analyzed and discussed.

Complementary filter design with three frequency bands: robot attitude estimation

This paper extents the by now classic sensor fusion complementary filter (CF) design, involving two sensors, to the case where three sensors that provide measurements in different bands are available. This paper shows that the use of classical CF techniques to tackle a generic three sensors fusion problem, based solely on their frequency domain characteristics, leads to a minimal realization, stable, sub-optimal solution, denoted as Complementary Filters3 (CF3). Then, a new approach for the estimation problem at hand is used, based on optimal linear Kalman filtering techniques. Moreover, the solution is shown to preserve the complementary property, i.e. the sum of the three transfer functions of the respective sensors add up to one, both in continuous and discrete time domains. This new class of filters are denoted as Complementary Kalman Filters3 (CKF3). The attitude estimation of a mobile robot is addressed, based on data from a rate gyroscope, a digital compass, and odometry. The experimental results obtained are reported.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

Prefácio: Vidas com história: a memória da guerra e a guerra da memória

“O livro que António Nogueira agora nos apresenta é uma versão muito abreviada da sua tese de doutoramento. Partes importantes dessa tese não constam desta publicação. No entanto, ao longo das páginas deste livro, é possível verificar como o autor procurou perscrutar como a instituição militar se adoptou à guerra colonial mas também as dificuldades que sentiu, nos anos finais da ditadura, em ajustar-se ao tipo de guerra que se desenvolvia em África (guerra subversiva). António Nogueira analisa ainda como um exército, cansado e esgotado pelo esforço de guerra, ao recorrer à incorporação de grande número de milicianos se torna bastante mais permeável à pressão social e contestação estudantil e política que se fazia sentir. E constata, entre outras coisas, como a necessidade de formar capitães do quadro permanente leva à adopção de modelos de formação que apostavam em cursos intensivos e acelerados que, segundo o autor, manifestavam graves deficiências eram pouco ajustados às realidades da guerra”. (do prefácio)