A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Optimal design for active damping in sandwich structures using the Direct MultiSearch method

This paper addresses the problem of optimal positioning of surface bonded piezoelectric patches in sandwich plates with viscoelastic core and laminated face layers. The objective is to maximize a set of modal loss factors for a given frequency range using multiobjective topology optimization. Active damping is introduced through co-located negative velocity feedback control. The multiobjective topology optimization problem is solved using the Direct MultiSearch Method. An application to a simply supported sandwich plate is presented with results for the maximization of the first six modal loss factors. The influence of the finite element mesh is analyzed and the results are, to some extent, compared with those obtained using alternative single objective optimization.

Design and construction of tunnels in zones subjected to high convergences

The economic development of a region depends on the speed that people and goods can travel. The reduction of people and goods travel time can be achieved by planning smooth road layouts, which are obtained by crossing natural obstacles such as hills, by tunneling at great depths, and allowing the reduction of the road alignment length. The stress state in rock masses at such depths, either because of the overburden or due to the tectonic conditions of the rock mass induces high convergences of the tunnel walls. These high convergence values are incompatible with the supports structural performance installed in the excavation stabilization. In this article it is intended to evaluate and analyze some of the solutions already implemented in several similar geological and geotechnical situations, in order to establish a methodological principle for the design of the tunnels included in a highway section under construction in the region influenced by the Himalayas, in the state of Himachal Pradesh (India) and referenced by "four laning of Kiratpur to Ner Chowk section".

On a self-start Darrieus wind turbine: blade design and field tests

This paper is about a design of an urban area Darrieus VAWT, having self-start ability due to an innovative profile design named EN0005, avoiding the need of extra components or external electricity feed-in. An approach is presented to study the ability of a blade profile to offer self-start ability. Methodologies applied for the blade body and for profile development are reported. Field tests and main conclusions are presented to persuade for the arrangement of this design. (C) 2015 Elsevier Ltd. All rights reserved.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.