35 resultados para stars : binary


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Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

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Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica

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This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

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Discrete data representations are necessary, or at least convenient, in many machine learning problems. While feature selection (FS) techniques aim at finding relevant subsets of features, the goal of feature discretization (FD) is to find concise (quantized) data representations, adequate for the learning task at hand. In this paper, we propose two incremental methods for FD. The first method belongs to the filter family, in which the quality of the discretization is assessed by a (supervised or unsupervised) relevance criterion. The second method is a wrapper, where discretized features are assessed using a classifier. Both methods can be coupled with any static (unsupervised or supervised) discretization procedure and can be used to perform FS as pre-processing or post-processing stages. The proposed methods attain efficient representations suitable for binary and multi-class problems with different types of data, being competitive with existing methods. Moreover, using well-known FS methods with the features discretized by our techniques leads to better accuracy than with the features discretized by other methods or with the original features. (C) 2013 Elsevier B.V. All rights reserved.

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The purpose of this paper is the design of an optoelectronic circuit based on a-SiC technology, able to act simultaneously as a 4-bit binary encoder or a binary decoder in a 4-to-16 line configurations and show multiplexer-based logical functions. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n multilayered structure produced by PECVD. To analyze it under information-modulated wave (color channels) and uniform irradiation (background) four monochromatic pulsed lights (input channels): red, green, blue and violet shine on the device. Steady state optical bias was superimposed separately from the front and the back sides, and the generated photocurrent was measured. Results show that the devices, under appropriate optical bias, act as reconfigurable active filters that allow optical switching and optoelectronic logic functions development providing the possibility for selective removal of useless wavelengths. The logic functions needed to construct any other complex logic functions are the NOT, and both or either an AND or an OR. Any other complex logic function that might be found can also be used as building blocks to achieve the functions needed for the retrieval of channels within the WDM communication link. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim