Simulação, em software adequado, da sintomatologia vibracional de avarias mecânicas de máquinas rotativas

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica na Área de Manutenção e Produção

Projeto de estrutura variante de um edifício de escritórios em Lisboa

Trabalho de Projecto para obtenção do grau de Mestre em Engenharia Civil na Área de Especialização de Estruturas

A bilhética dos transportes de passageiros na nuvem computacional

Relatório de Projeto realizado para obtenção do grau de Mestre em Engenharia Informática e de Computadores

Caracterização e modelação de fissuras em edifícios utilizando 3D laser scanning, com vista à sua reabilitação

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Civil

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

A Compact and Scalable RNS Architecture

Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013

Buying behavior and competition in the software market

In the actual world, the impact of the software buying decisions has a rising relevance in social and economic terms. This research tries to explain it focusing on the organizations buying decisions of Operating Systems and Office Suites for personal computers and the impact on the competition between incumbent and alternative players in the market in these software categories, although the research hypotheses and conclusions may extend to other software categories and platforms. We concluded that in this market beside brand image, product features or price, other factors could have influence in the buying choices. Network effect, switching costs, local network effect, lock-in or consumer heterogeneity all have influence in the buying decision, protecting the incumbent and making it difficult for the competitive alternatives, based mainly on product features and price, to gain market share to the incumbent. This happens in a stronger way in the Operating Systems category.

Influencing factors on the buying behavior in the software market

The case of desktop Operating System and Office Suite choices considering Proprietary and Open Source Software alternatives.

Estimação de cobertura rádio em comunicações ferroviárias

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

An efficient scalable RNS architecture for large dynamic ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

Corrugated horn antenna for a CosmoGal satellite with reduced dimensions

This paper presents the design methodology for the creation of corrugated horn antennas for the CosmoGal satellite. The mission will collect the radiation of the cosmic microwave background, by a radiometer in three different radio astronomy frequency bands (10.6-10.7GHz; 15.35-15.4GHz; 23.6-24GHz). It is discussed the design of several types of horns, simulated with the CST software. The best result points to a choked Gaussian corrugated horn antenna, with directivity of 23 dBi, side lobes 35 dB below and cross polarization better than -45 dB. Plus, with the advantage of having a small dimension, with a total length of only 7.43λ © 2014 IEEE.

Neighbour list optimization for real LTE radio network

With the increasing complexity of current networks, it became evident the need for Self-Organizing Networks (SON), which aims to automate most of the associated radio planning and optimization tasks. Within SON, this paper aims to optimize the Neighbour Cell List (NCL) for Long Term Evolution (LTE) evolved NodeBs (eNBs). An algorithm composed by three decisions were were developed: distance-based, Radio Frequency (RF) measurement-based and Handover (HO) stats-based. The distance-based decision, proposes a new NCL taking account the eNB location and interference tiers, based in the quadrants method. The last two algorithms consider signal strength measurements and HO statistics, respectively; they also define a ranking to each eNB and neighbour relation addition/removal based on user defined constraints. The algorithms were developed and implemented over an already existent radio network optimization professional tool. Several case studies were produced using real data from a Portuguese LTE mobile operator. © 2014 IEEE.

Performance comparison of a VDFLL versus VDLL and scalar GNSS receiver architectures in Harsh scenarios

We analyze the advantages and drawbacks of a vector delay/frequency-locked loop (VDFLL) architecture regarding the conventional scalar and the vector delay-locked loop (VDLL) architectures for GNSS receivers in harsh scenarios that include ionospheric scintillation, multipath, and high dynamics motion. The VDFLL is constituted by a bank of code and frequency discriminators feeding a central extended Kaiman filter (EKF) that estimates the receiver's position, velocity, and clock bias. Both code and frequency loops are closed vectorially through the EKF. The VDLL closes the code loop vectorially and the phase loops through individual PLLs while the scalar receiver closes both loops by means of individual independent PLLs and DLLs.

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.