Palaeomagnetic study of a subaerial volcanic ridge (São Jorge Island, Azores) for the cobb mountain subhron, volcano flank instability and tectonomagmatic implications

We present a palaeomagnetic study on 38 lava flows and 20 dykes encompassing the past 1.3 Myr on S. Jorge Island (Azores ArchipelagoNorth Atlantic Ocean). The sections sampled in the southeastern and central/western parts of the island record reversed and normal polarities, respectively. They indicate a mean palaeomagnetic pole (81.3 degrees N, 160.7 degrees E, K= 33 and A95= 3.4 degrees) with a latitude shallower than that expected from Geocentric Axial Dipole assumption, suggesting an effect of non-dipolar components of the Earth magnetic field. Virtual Geomagnetic Poles of eight flows and two dykes closely follow the contemporaneous records of the Cobb Mountain Subchron (ODP/DSDP programs) and constrain the age transition from reversed to normal polarity at ca. 1.207 +/- 0.017 Ma. Volcano flank instabilities, probably related to dyke emplacement along an NNWSSE direction, led to southwestward tilting of the lava pile towards the sea. Two spatially and temporally distinct dyke systems have been recognized on the island. The eastern is dominated by NNWSSE trending dykes emplaced before the end of the Matuyama Chron, whereas in the central/western parts the eruptive fissures oriented WNWESE controlled the westward growth of the S. Jorge Island during the Brunhes Chron. Both directions are consistent with the present-day regional stress conditions deduced from plate kinematics and tectonomorphology and suggest the emplacement of dykes along pre-existing fractures. The distinct timing and location of each dyke system likely results from a slight shift of the magmatic source.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.