20 resultados para Wood Architecture


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One Plus Sequential Air Sampler—Partisol was placed in a small village (Foros de Arrão) in central Portugal to collect PM10 (particles with an aerodynamic diameter below 10 μm), during the winter period for 3 months (December 2009–March 2010). Particles masses were gravimetrically determined and the filters were analyzed by instrumental neutron activation analysis to assess their chemical composition. The water-soluble ion compositions of the collected particles were determined by Ion-exchange Chromatography. Principal component analysis was applied to the data set of chemical elements and soluble ions to assess the main sources of the air pollutants. The use of both analytical techniques provided information about elemental solubility, such as for potassium, which was important to differentiate sources.

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In this review paper different designs based on stacked p-i'-n-p-i-n heterojunctions are presented and compared with the single p-i-n sensing structures. The imagers utilise self-field induced depletion layers for light detection and a modulated laser beam for sequential readout. The effect of the sensing element structure, cell configurations (single or tandem), and light source properties (intensity and wavelength) are correlated with the sensor output characteristics (light-to-dark sensivity, spatial resolution, linearity and S/N ratio). The readout frequency is optimized showing that scans speeds up to 104 lines per second can be achieved without degradation in the resolution. Multilayered p-i'-n-p-i-n heterostructures can also be used as wavelength-division multiplexing /demultiplexing devices in the visible range. Here the sensor element faces the modulated light from different input colour channels, each one with a specific wavelength and bit rate. By reading out the photocurrent at appropriated applied bias, the information is multiplexed or demultiplexed and can be transmitted or recovered again. Electrical models are present to support the sensing methodologies.

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This paper concerns the study of biocides application in old timber structures of maritime pine (Pinus pinaster Ail.), previously impregnated with other products. A method was developed in laboratory to determine in situ the penetration depth of a product applied superficially. As initial treatment, three traditional products for sawn timber for buildings were used and, for new treatments, two newer, more environmentally benign products were used. Their ability to penetrate the pre-treated surfaces was evaluated after 1, 2 and 3 applications at 24 hours intervals and the results obtained are presented. Finally, the applicability of the developed test to the in-situ evaluation of timber structures is also discussed.

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A new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of theproposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).

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The kraft pulps produced from heartwood and sapwood of Eucalyptus globulus at 130 degrees C, 150 degrees C, and 170 degrees C were characterized by wet chemistry (total lignin as sum of Klason and soluble lignin fractions) and pyrolysis (total lignin denoted as py-lignin). The total lignin content obtained with both methods was similar. In the course of delignification, the py-lignin values were higher (by 2 to 5%) compared to Klason values, which is in line with the importance of soluble lignin for total lignin determination. Pyrolysis analysis presents advantages over wet chemical procedures, and it can be applied to wood and pulps to determine lignin contents at different stages of the delignification process. The py-lignin values were used for kinetic modelling of delignification, with very high predictive value and results similar to those of modelling using wet chemical determinations.

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A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 x 4 and 2 x 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120x concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 x 7,680 @ 30 fps).

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A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

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Conferência: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)- Jun 05-07, 2013

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When timber elements in heritage buildings are moderately degraded by fungi and assuming underlying moisture problems have been solved, two actions can be taken: i) use a biocide to stop fungal activity; ii) consolidate the degraded elements so that the timber keeps on fulfilling its structural and decorative functions. The aim of this work is to investigate the mechanical performance of maritime pine wood degraded by fungi after being treated with a biocide followed by impregnation with a polymer product. Three commercially available products were used: a boron water-based biocide, an acrylic consolidant and an epoxy-based consolidant. Treated and consolidated specimens were subjected to mechanical tests: axial compression test (NP 618), static surface hardness (ISO 3350) and bending test (NP 619). Sets of replicates were subjected to an evaporation ageing test (EN 73) after application of the products and also tested for mechanical behaviour. An increase in mechanical strength was observed for both consolidants with no significant influence from the previous use of biocide product. The specimens subjected to ageing showed a slightly better general mechanical performance.

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This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

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A noncoherent vector delay/frequency-locked loop (VDFLL) architecture for GNSS receivers is proposed. A bank of code and frequency discriminators feeds a central extended Kalman filter that estimates the receiver's position and velocity, besides the clock error. The VDFLL architecture performance is compared with the one of the classic scalar receiver, both for scintillation and multipath scenarios, in terms of position errors. We show that the proposed solution is superior to the conventional scalar receivers, which tend to lose lock rapidly, due to the sudden drops of the received signal power.

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A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

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This paper presents a layered Smart Grid architecture enhancing security and reliability, having the ability to act in order to maintain and correct infrastructure components without affecting the client service. The architecture presented is based in the core of well design software engineering, standing upon standards developed over the years. The layered Smart Grid offers a base tool to ease new standards and energy policies implementation. The ZigBee technology implementation test methodology for the Smart Grid is presented, and provides field tests using ZigBee technology to control the new Smart Grid architecture approach. (C) 2014 Elsevier Ltd. All rights reserved.

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This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

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A non-coherent vector delay/frequency-locked loop architecture for GNSS receivers is proposed. Two dynamics models are considered: PV (position and velocity) and PVA (position, velocity, and acceleration). In contrast with other vector architectures, the proposed approach does not require the estimation of signals amplitudes. Only coarse estimates of the carrier-to-noise ratios are necessary.