A biomimetic piezoelectric pump: Computational and experimental characterization

Flow pumps have been developed for classical applications in Engineering, and are important instruments in areas such as Biology and Medicine. Among applications for this kind of device we notice blood pump and chemical reagents dosage in Bioengineering. Furthermore, they have recently emerged as a viable thermal management solution for cooling applications in small-scale electronic devices. This work presents the performance study of a novel principle of a piezoelectric flow pump which is based oil the use of a bimorph piezoelectric actuator inserted in fluid (water). Piezoelectric actuators have some advantages over classical devices, such as lower noise generation and ease of miniaturization. The main objective is the characterization of this piezoelectric pump principle through computational simulations (using finite element software), and experimental tests through a manufactured prototype. Computational data, Such as flow rate and pressure curves, have also been compared with experimental results for validation purposes. (C) 2009 Elsevier B.V. All rights reserved.

Piezoresistive sensor design using topology optimization

Piezoresistive materials, materials whose resistivity properties change when subjected to mechanical stresses, are widely utilized in many industries as sensors, including pressure sensors, accelerometers, inclinometers, and load cells. Basic piezoresistive sensors consist of piezoresistive devices bonded to a flexible structure, such as a cantilever or a membrane, where the flexible structure transmits pressure, force, or inertial force due to acceleration, thereby causing a stress that changes the resistivity of the piezoresistive devices. By applying a voltage to a piezoresistive device, its resistivity can be measured and correlated with the amplitude of an applied pressure or force. The performance of a piezoresistive sensor is closely related to the design of its flexible structure. In this research, we propose a generic topology optimization formulation for the design of piezoresistive sensors where the primary aim is high response. First, the concept of topology optimization is briefly discussed. Next, design requirements are clarified, and corresponding objective functions and the optimization problem are formulated. An optimization algorithm is constructed based on these formulations. Finally, several design examples of piezoresistive sensors are presented to confirm the usefulness of the proposed method.

Effect of nitrogen on the corrosion-erosion synergism in an austenitic stainless steel

High temperature gas nitrided AISI 304L austenitic stainless steel containing 0.55 wt% N in solid solution, was corrosion, erosion and corrosion-erosion tested in a jet-like device, using slurry composed of 3.5% NaCl and quartz particles. Scanning electron microscopy analysis of the damaged surfaces, mass loss measurements and electrochemical test results were used to understand the effect of nitrogen on the degradation mechanisms. Increasing the nitrogen content improved the corrosion, erosion and corrosion-erosion resistance of the AISI 304L austenitic stainless steel. Smoother wear mark contours observed on the nitrided surfaces indicate a positive effect of nitrogen on the reduction of the corrosion-erosion synergism. (C) 2011 Elsevier Ltd. All rights reserved.

Controlling the luminescence properties of poly(p-phenylene vinylene) entrapped in Langmuir and Langmuir-Blodgett films of stearic acid

Properties of hybrid films can be enhanced if their molecular architecture is controlled. In this paper, poly (p-phenylene vinylene) was mixed with stearic acid in order to form stable hybrid Langmuir monolayers. Surface properties of these films were investigated with measurements of surface pressure, and also with polarization modulation infrared reflection-absorption spectroscopy (PM-IRRAS). The films were transferred from the air-water interface to solid supports through the Langmuir-Blodgett technique, and the viability of the film as optical device was investigated with fluorescence spectroscopy. Comparing the fluorescent spectra for the polymer in solution, as a casting film, and as an LB film, the emission bands for LB films were narrower and appeared at lower wavelengths. The interactions between the film components and the design for the LB film may take advantage of the method to immobilize luminescent polymers in mixed ultrathin films adsorbed in solid matrices. (C) 2011 Elsevier B.V. All rights reserved.

EROSION-CORROSION SYNERGISM OF AN AISI 410 MARTENSITIC STAINLESS STEEL

In this work, the behavior of an AISI 410 martensitic stainless steel under corrosion-erosion conditions is evaluated. Quenched and tempered samples were used for the wear test, using a low velocity jet-like device connected to a potentiostat. Potentiodynamic polarization curves were obtained with the electrolyte in static state, with flow conditions and under corrosion-erosion, adding quartz particles to the electrolyte. In addition, mass loss measurements under erosion and corrosion-erosion conditions were carried out. The topography of the surfaces was examined after the wear tests, using optical and scanning electron microscopy. This information, together with the results of mass losses and the electrochemical tests were used to establish the degradation mechanisms of the stainless steels under different testing conditions. The results showed that synergism is a significant part of the degradation process of this steel (66.5%) and that the mass removal process of steel was controlled by corrosion assisted by erosion.

DEVELOPMENT OF A MICRO-HEAT EXCHANGER WITH STACKED PLATES USING LTCC TECHNOLOGY

A green ceramic tape micro-heat exchanger was developed using Low Temperature Co-fired Ceramics technology (LTCC). The device was designed by using Computational Aided Design software and simulations were made using a Computational Fluid Dynamics package (COMSOL Multiphysics) to evaluate the homogeneity of fluid distribution in the microchannels. Four geometries were proposed and simulated in two and three dimensions to show that geometric details directly affect the distribution of velocity in the micro-heat exchanger channels. The simulation results were quite useful for the design of the microfluidic device. The micro-heat exchanger was then constructed using the LTCC technology and is composed of five thermal exchange plates in cross-flow arrangement and two connecting plates, with all plates stacked to form a device with external dimensions of 26 x 26 x 6 mm(3).

Performance of a solar energy powered falling film evaporator with film promoter

A solar energy powered failing film evaporator with film promoter was developed for concentrating diluted solutions (industrial effluents). The procedure proposed here does not emit CO(2), making it a viable alternative to the method of concentrating solutions that uses vapor as a heat source and releases CO(2) from burning fuel oil in a furnace, in direct opposition to the carbon reduction agreement established by the Kyoto protocol. This novel device consists of the following components: a flat plate solar collector with adjustable inclination, a film promoter (adhering to the collector), a liquid distributor, a concentrate collector. and accessories. The evaporation rate of the device was found to be affected both by the inclination of the collector and by the feed flow. The meteorological variables cannot be controlled, but were monitored constantly to ascertain the behavior of the equipment in response to the variations occurring throughout the day. Higher efficiencies were attained when the inclination of the collector was adjusted monthly, showing up to 36.4% higher values than when the collector remained in a fixed position. (c) 2008 Elsevier Ltd. All rights reserved.

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

Trapezoidal SOI FinFET analog parameters` dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Cryogenic operation of FinFETs aiming at analog applications

FinFETs are recognized as promising candidates for the CMOS nanometer era. In this paper the most recent results for cryogenic operation of FinFETs will be demonstrated with special emphasis on analog applications. Threshold voltage, subthreshold slope and carrier mobility will be studied. Also some important figures of merit for analog circuit operation as for readout electronics, such as transconductance, output conductance and intrinsic voltage gain will be covered. It is demonstrated that the threshold voltage of undoped narrow FinFETs is less temperature-dependent than for a planar single-gate device with similar doping concentration. The temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L = 90 nm FinFET is degraded by 2 dB when the temperature reduces from 300 K to 100 K. (C) 2009 Elsevier Ltd. All rights reserved.

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.