An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

Perceptual user interface framework for immersive information retrieval environments (An experimental framework for testing and rapid iteration)

The use of perceptual inputs is an emerging area within HCI that suggests a developing Perceptual User Interface (PUI) that may prove advantageous for those involved in mobile serious games and immersive social network environments. Since there are a large variety of input devices, software platforms, possible interactions, and myriad ways to combine all of the above elements in pursuit of a PUI, we propose in this paper a basic experimental framework that will be able to standardize study of the wide range of interactive applications for testing efficacy in learning or information retrieval and also suggest improvements to emerging PUIs by enabling quick iteration. This rapid iteration will start to define a targeted range of interactions that will be intuitive and comfortable as perceptual inputs, and enhance learning and information retention in comparison to traditional GUI systems. The work focuses on the planning of the technical development of two scenarios, and the first steps in developing a framework to evaluate these and other PUIs for efficacy and pedagogy.

Asynchronous distributed parallelization of mobile network optimization algorithms

It has been years since the introduction of the Dynamic Network Optimization (DNO) concept, yet the DNO development is still at its infant stage, largely due to a lack of breakthrough in minimizing the lengthy optimization runtime. Our previous work, a distributed parallel solution, has achieved a significant speed gain. To cater for the increased optimization complexity pressed by the uptake of smartphones and tablets, however, this paper examines the potential areas for further improvement and presents a novel asynchronous distributed parallel design that minimizes the inter-process communications. The new approach is implemented and applied to real-life projects whose results demonstrate an augmented acceleration of 7.5 times on a 16-core distributed system compared to 6.1 of our previous solution. Moreover, there is no degradation in the optimization outcome. This is a solid sprint towards the realization of DNO.