2 resultados para digital architecture
em WestminsterResearch - UK
Resumo:
The construction industry wants graduate employees skilled in relationship building and information technology and communications (ITC). Much of the relationship building at universities has evolved through technology. Government and the ITC industry fund lobby groups to influence both educational establishments and Government to incorporate more ITC in education _ and ultimately into the construction industry. This influencing ignores the technoskeptics’ concerns about student disengagement through excessive online distractions. Construction studies students (n=64) and lecturers (n=16) at a construction university were surveyed to discover the impact of the use and applications of ITC. Contrary to Government and industry technopositivism, construction students and lecturers preferred hard copy documents to online feedback for assignments and marking, more human interface and less technological substitution and to be on campus for lectures and face-to-face meetings rather than viewing on-screen. ITC also distracted users from tasks which, in the case of students, prevented the development of the concentration and deep thinking which a university education should deliver. The research findings are contrary to the promotions of Government, ITC industry and ITC departments and have implications for construction employers where a renewed focus on human communication should mean less stress, fewer delays and cost overruns.
Resumo:
A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.