I Stood Up: Social Design in Practice

Through practice-based research, we explore how interdisciplinary design projects can function to address social issues concerning environmental and social problems. Using two case studies developed between London in the United Kingdom, and Delhi and Ahmedabad in India, we discuss the importance of engagement with the people who the design ultimately serves. Finally, we argue that design concerned with complex social problems require equally complex, multidimensional responses, informed by bodies of knowledge, practices and approaches that lie outside of traditional design approaches.

Methods for the transfer function design of multiple narrow-band bandpass sigma-delta modulators

This paper presents the design analysis of novel tunable narrow-band bandpass sigma-delta modulators, which can achieve concurrent multiple noise-shaping for multi-tone input signals. Four different design methodologies based on the noise transfer functions of comb filters, slink filters, multi-notch filters and fractional delay comb filters are applied for the design of these multiple-band sigma-delta modulators. The latter approach utilises conventional comb filters in conjunction with FIR, or allpass IIR fractional delay filters, to deliver the desired nulls for the quantisation noise transfer function. Detailed simulation results show that FIR fractional delay comb filter-based sigma-delta modulators tune accurately to most centre frequencies, but suffer from degraded resolution at frequencies close to Nyquist. However, superior accuracies are obtained from their allpass IIR fractional delay counterpart at the expense of a slight shift in noise-shaping bands at very high frequencies. The merits and drawbacks of each technique for the various sigma-delta topologies are assessed in terms of in-band signal-to-noise ratios, accuracy of tunability and coefficient complexity for ease of implementation.

On the performance of a blind source separation based I/Q-corrector

I and Q Channel phase and gain mismatches are of great concern in communications receiver design. In this paper we carry out a detailed performance analysis of the Blind-Source Seperation (BSS) based imbalance compensation structure. The results indicate that the BSS structure can offer adequate performance for most communication systems. Since the compensation is carried out before any modulation specific processing, the proposed compensation method works with all standard modulation formats.

Adaptive compensation of analog front-end I/Q mismatches in digital receivers

I and Q Channel phase and gain misniatches are of great concern in communications receiver design. In this paper we analyse the effects of I and Q channel mismatches and propose a low-complexity blind adaptive algorithm to minimize this problem. The proposed solution consists of two, 2-tap adaptive filters, arranged in Adaptive Noise Canceller (ANC) set-up, with the output of one cross-fed to the input of the other. The system works as a de-correlator eliminating I and Q mismatch errors.

Efficient low-power design and implementation of IQ-imbalance compensator using early termination

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50 % for 32-PSK and 37-58 % for 64-QAM modulated signals.

A new bulk-driven input stage design for sub 1-volt CMOS op-amps

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V/sub T0/+ 3V/sub DSsat/) to the maximum allowed for the CMOS process, as well as preventing latch-up.

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.

Design of a power-aware digital image rejection receiver

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Literature Review WM9: Part I - urban freight transport, carried out as part of Work Module 1, Green Logistics Project

The review illustrates the importance of road movements in goods distribution in urban areas. It highlights the major economic, environmental and social impacts associated with this freight activity and reviews policy options available to those responsible for regulation. A wide range of possible solutions to problems posed by urban freight operations are also covered including approaches related to: consolidation, facilities, vehicle design, information capture and utilisation, and non-road modes.

Program slice metrics and their potential role in DSL design, position paper

The advantages a DSL and the benefits its use potentially brings imply that informed decisions on the design of a domain specific language are of paramount importance for its use. We believe that the foundations of such decisions should be informed by analysis of data empirically collected from systems to highlight salient features that should then form the basis of a DSL. To support this theory, we describe an empirical study of a large OSS called Barcode, written in C, and from which we collected two well-known 'slice' based metrics. We analyzed multiple versions of the system and sliced its functions in three separate ways (i.e., input, output and global variables). The purpose of the study was to try and identify sensitivities and traits in those metrics that might inform features of a potential slice-based DSL. Results indicated that cohesion was adversely affected through the use of global variables and that appreciation of the role of function inputs and outputs can be revealed through slicing. The study presented is motivated primarily by the problems with current tools and interfaces experienced directly by the authors in extracting slicing data and the need to promote the benefits that analysis of slice data and slicing in general can offer.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.

NFC RF Analog Challenge and Enhanced High Speed Transmitter Design

This paper investigates the inherent radio frequency analog challenges associated with near field communication systems. Furthermore, the paper presents a digital based sigma-delta modulator for near field communication transmitter implementations. The proposed digital transmitter architecture is designed to best support data intensive applications requiring higher data rates and complex modulation schemes. An NFC transmitter based on a single-bit sigma-delta DAC is introduced, and then the multi-bit extension with necessary simulation results are presented to confirm the suitability of the architecture for near field communication high speed applications.