5 resultados para continuous labelling

em WestminsterResearch - UK


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Next generation Global Navigation Satellite System (GNSS) receivers will operate in multiple navigation bands. An efficient way to achieve this with lower power and cost is to employ BandPass Sampling (BPS); nevertheless, the sampling operation injects large amounts of jitter noise, which degrades the performance of the receiver. Continuous–Time (CT) Delta–Sigma (ΔΣ) modulators are capable of suppressing this noise but the impact of clock jitter at the output of the Digital– to–Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for describing clock jitter in GNSS receivers when a CT–ΔΣ modulator is utilized for Analog–to–Digital Conversion (ADC). The validity of the presented approach is verified through time–domain simulations using a behavioural model of the fourth–order CT–ΔΣ modulator with 1–bit NRZ DAC feedback pulse.

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This paper applies Gaussian estimation methods to continuous time models for modelling overseas visitors into the UK. The use of continuous time modelling is widely used in economics and finance but not in tourism forecasting. Using monthly data for 1986–2010, various continuous time models are estimated and compared to autoregressive integrated moving average (ARIMA) and autoregressive fractionally integrated moving average (ARFIMA) models. Dynamic forecasts are obtained over different periods. The empirical results show that the ARIMA model performs very well, but that the constant elasticity of variance (CEV) continuous time model has the lowest root mean squared error (RMSE) over a short period.

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Energy-using Products (EuPs) contribute significantly to the United Kingdom’s CO2 emissions, both in the domestic and non-domestic sectors. Policies that encourage the use of more energy efficient products (such as minimum performance standards, energy labelling, enhanced capital allowances, etc.) can therefore generate significant reductions in overall energy consumption and hence, CO2 emissions. While these policies can impose costs on the producers and consumers of these products in the short run, the process of product innovation may reduce the magnitude of these costs over time. If this is the case, then it is important that the impacts of innovation are taken into account in policy impact assessments. Previous studies have found considerable evidence of experience curve effects for EuP categories (e.g. refrigerators, televisions, etc.), with learning rates of around 20% for both average unit costs and average prices; similar to those found for energy supply technologies. Moreover, the decline in production costs has been accompanied by a significant improvement in the energy efficiency of EuPs. Building on these findings and the results of an empirical analysis of UK sales data for a range of product categories, this paper sets out an analytic framework for assessing the impact of EuP policy interventions on consumers and producers which takes explicit account of the product innovation process. The impact of the product innovation process can be seen in the continuous evolution of the energy class profiles of EuP categories over time; with higher energy classes (e.g. A, A+, etc.) entering the market and increasing their market share, while lower classes (e.g. E, F, etc.) lose share and then leave the market. Furthermore, the average prices of individual energy classes have declined over their respective lives, while new classes have typically entered the market at successively lower “launch prices”. Based on two underlying assumptions regarding the shapes of the “lifecycle profiles” for the relative sales and the relative average mark-ups of individual energy classes, a simple simulation model is developed that can replicate the observed market dynamics in terms of the evolution of market shares and average prices. The model is used to assess the effect of two alternative EuP policy interventions – a minimum energy performance standard and an energy-labelling scheme – on the average unit cost trajectory and the average price trajectory of a typical EuP category, and hence the financial impacts on producers and consumers.

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This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.