7 resultados para Performance evolution due time
em WestminsterResearch - UK
Resumo:
Next generation Global Navigation Satellite System (GNSS) receivers will operate in multiple navigation bands. An efficient way to achieve this with lower power and cost is to employ BandPass Sampling (BPS); nevertheless, the sampling operation injects large amounts of jitter noise, which degrades the performance of the receiver. Continuous–Time (CT) Delta–Sigma (ΔΣ) modulators are capable of suppressing this noise but the impact of clock jitter at the output of the Digital– to–Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for describing clock jitter in GNSS receivers when a CT–ΔΣ modulator is utilized for Analog–to–Digital Conversion (ADC). The validity of the presented approach is verified through time–domain simulations using a behavioural model of the fourth–order CT–ΔΣ modulator with 1–bit NRZ DAC feedback pulse.
Resumo:
In this paper, the performance and convergence time comparisons of various low-complexity LMS algorithms used for the coefficient update of adaptive I/Q corrector for quadrature receivers are presented. We choose the optimum LMS algorithm suitable for low complexity, high performance and high order QAM and PSK constellations. What is more, influence of the finite bit precision on VLSI implementation of such algorithms is explored through extensive simulations and optimum wordlengths established.
Resumo:
This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques.
Resumo:
Global navigation satellite system (GNSS) receivers require solutions that are compact, cheap and low-power, in order to enable their widespread proliferation into consumer products. Furthermore, interoperability of GNSS with non-navigation systems, especially communication systems will gain importance in providing the value added services in a variety of sectors, providing seamless quality of service for users. An important step into the market for Galileo is the timely availability of these hybrid multi-mode terminals for consumer applications. However, receiver architectures that are amenable to high-levels of integration will inevitably suffer from RF impairments hindering their easy widespread use in commercial products. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments and develops algorithms that can compensate for them in the DSP domain at the base band with complexity-reduced hardware overheads, hence, paving the way for low-power, highly integrated multi-mode GNSS receivers.
Resumo:
In this paper, we carry out a detailed performance analysis of the blind source separation based I/Q corrector operating at the baseband. Performance of the digital I/Q corrector is evaluated not only under time-varying phase and gain errors but also in the presence of multipath and Rayleigh fading channels. Performance under low-SNR and different modulation formats and constellation sizes is also evaluated. What is more, BER improvement after correction is illustrated. The results indicate that the adaptive algorithm offers adequate performance for most communication applications hence, reducing the matching requirements of the analog front-end enabling higher levels of integration.
Resumo:
Sweroside, a major active iridoid in Swertia pseudochinensis Hara, is recognized as an effective agent in the treatment of liver injury. Based on previous reports, the relatively short half-life (64 min) and poor bioavailability (approximately 0.31%) in rats suggested that not only sweroside itself but also its metabolites could be responsible for the observed hepato-protective effect. However, few studies have been carried out on the metabolism of sweroside. Therefore, the present study aimed at identifying the metabolites of sweroside in rat urine after a single oral dose (100 mg/kg). With ultra-high-performance liquid chromatography coupled with electrospray ionization quadrupole time-of-flight tandem mass spectrometry (UHPLC/Q-TOF-MS), the metabolic profile revealed 11 metabolites in rat urine, including phase I, phase II and aglycone-related products. The chemical structures of metabolites were proposed based on accurate mass measurements of protonated or deprotonated molecules and their fragmentation patterns. Our findings showed that the aglycone of sweroside (M05) and its glucuronide conjugate (M06) were principal circulating metabolites in rats. While several other metabolic transformations, occurring via reduction, N-heterocyclization and N-acetylation after deglycosylation, were also observed. Two metabolites (M05 and M06) were isolated from the rat urine for structural elucidation and identifcation of reaction sites. Both M05 and M06 were characterized by 1H, 13C and two-dimensional nuclear magnetic resonance (NMR) spectroscopy. UHPLC/Q-TOF-MS analysis has provided an important analytical platform to gather metabolic profile of sweroside.
Resumo:
This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.