An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute a 256-point complex FFT in 102.4 μs excluding data input and output processes.

An integrated 256-point complex FFT processor for real-time spectrum analysis and measurement

This paper describes in detail the design of a custom CMOS Fast Fourier Transform (FFT) processor for computing 256-point complex FFT. The FFT is well suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute 256-complex point FFT in 25.6 μs excluding data input and output processes.

Narrow-band variable center frequency single-loop and multistage sigma-delta modulators for bandpass signals

Oversampled narrow-band single-loop and multistage resonator-based bandpass sigma-delta (Σ-Δ) modulators that can accommodate different passband center to sampling frequency ratios are reported. These tunable bandpass configurations are designed by analytically determining and subsequently verifying through detailed empirical simulations the required compensation hardware to deliver enhanced noise-shaping. It is demonstrated that comparatively superior in-band signal-to-noise ratios and dynamic ranges are attributed to the inclusion of appropriate digital feedforward and feedback compensators within these structures.

Quantization effects in the polyphase N-path IIR structure

Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL.

Tunable centre frequency resonator based bandpass Σ-Δ modulators

This paper presents a methodology for the design of oversampled narrow-band single-loop and multi-stage resonator-based bandpass Σ-Δ modulators that can accommodate different passband centre to sampling frequency ratios. These tunable bandpass configurations are designed by analytically determining the required compensation hardware to deliver good resolution. Thorough simulations demonstrate that comparatively superior in-band signal-to-noise ratios (SNRs) and dynamic ranges (DRs) are attributed to the inclusion of appropriate feedforward and feedback compensators within these structures.

Towards an Application-Specific Thermal Energy Model of Current Processors

Recent developments of high-end processors recognize temperature monitoring and tuning as one of the main challenges towards achieving higher performance given the growing power and temperature constraints. To address this challenge, one needs both suitable thermal energy abstraction and corresponding instrumentation. Our model is based on application-specific parameters such as power consumption, execution time, and asymptotic temperature as well as hardware-specific parameters such as half time for thermal rise or fall. As observed with our out-of-band instrumentation and monitoring infrastructure, the temperature changes follow a relatively slow capacitor-style charge-discharge process. Therefore, we use the lumped thermal model that initiates an exponential process whenever there is a change in processor’s power consumption. Initial experiments with two codes – Firestarter and Nekbone – validate our thermal energy model and demonstrate its use for analyzing and potentially improving the application-specific balance between temperature, power, and performance.