2 resultados para Input timedelays

em WestminsterResearch - UK


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This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V/sub T0/+ 3V/sub DSsat/) to the maximum allowed for the CMOS process, as well as preventing latch-up.

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This paper presents a comparative study of complex single-bit and multi-bit sigma-delta modulators that are capable of providing concurrent multiple-band noise-shaping for multi-tone narrow-band input signals. The concepts applied for the three design methodologies are based on the noise transfer functions of complex comb, complex slink and complex multi-notch filters.